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0910-A22-05

Ambipolar Thin-Film Transistors Fabricated by PECVD Nanocrystalline Silicon Czang-Ho Lee, Andrei Sazonov, Mohammad R. E. Rad, G. Reza Chaji, and Arokia Nathan Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, N2L 3G1, Canada ABSTRACT We report on directly deposited plasma-enhanced chemical vapor deposition (PECVD) nanocrystalline silicon (nc-Si:H) ambipolar thin-film transistors (TFTs) fabricated at 260 ºC. The ambipolar operation is achieved adopting Cr metal contacts with high-quality nc-Si:H channel layer, which creates highly conductive Cr silicided drain/source contacts, reducing both electron and hole injection barriers. The n-channel nc-Si:H TFTs show a field-effect electron mobility (µeFE) of 150 cm2/Vs, threshold voltage (VT) ~ 2 V, subthreshold slope (S) ~0.3 V/dec, and ON/OFF current ratio of more than 107, while the p-channel nc-Si:H TFTs show a field-effect hole mobility (µhFE) of 26 cm2/Vs, VT ~ −3.8 V, S ~0.25 V/dec, and ON/OFF current ratio of more than 106. Complementary metal-oxide-semiconductor (CMOS) logic integrated with two ambipolar nc-Si:H TFTs shows reasonable transfer characteristics. The results presented here demonstrate that low-temperature nc-Si:H TFT technology is feasible for total integration of active-matrix TFT backplanes. INTRODUCTION Low-temperature (~300 ºC) plasma-enhanced chemical vapor deposition (PECVD) nanocrystalline silicon (nc-Si:H) thin-film transistors (TFTs) have recently received much attention as active devices for use in flat panel electronics due to their high device mobility (10−150 cm2/Vs for electron channel) [1, 2] and good device stability [3] compared to PECVD hydrogenated amorphous silicon (a-Si:H) TFTs. Another important merit of nc-Si:H TFT technology over that of a-Si:H is also its capability to fabricate p-channel as well as n-channel devices [2, 4] like in polycrystalline silicon (poly-Si) TFT technology. This directly enables monolithic integration of complementary metal-oxide-semiconductor (CMOS) circuits [4]. This technology is highly demanded in the integrated-circuit (IC) industry pursuing low-power consumption for readout electronics fabrication on the same substrate with a pixelated TFT array for high-density active-matrix TFT backplanes. However, to realize the building blocks pertinent to complementary digital circuits, high hole device mobility nc-Si:H TFTs are needed. To date, hole channel mobility values in the range of 0.023−0.25 cm2/Vs have been reported in nc-Si:H TFTs [2, 4], but these values are two to four orders of magnitude lower than electron channel mobility values (10−150 cm2/Vs) reported [1, 2]. Schottky-contact MOS transistors have been suggested for downscaling of Si electronics [5, 6] because the ultra-shallow drain/source junction with very low contact resistance (Rcontact) can be made using a simplified process. Er [5] for n-channel and Pt [6] for p-channel operation are widely employed as Schottky drain/source metals, because silicided ErSi and PtSi show low Schottky barrier height (qφ