An asynchronous protocol for virtual factory simulation on shared memory multiprocessor systems
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An asynchronous protocol for virtual factory simulation on shared memory multiprocessor systems B-P Gan1 and SJ Turner*2 1
Gintic Institute of Manufacturing Technology and 2University of Exeter
The development of parallel simulation technology is seen as an enabler for the implementation of the virtual factory concept, the integrated simulation of all the systems in a factory. One important parallel simulation protocol, the asynchronous deadlock avoidance algorithm proposed by Chandy, Misra, and Bryant, has usually been discussed in the context of distributed memory systems. Also, null messages have normally been associated with this approach for deadlock avoidance. This paper presents a new implementation of the CMB protocol designed for shared memory multiprocessor systems. We have successfully used this protocol, which we call the CMB-SMP protocol, to achieve useful speedups in a manufacturing simulation application, despite the ®ne granularity of event processing. The implementation eliminates the need for sending null messages, without causing deadlock in the simulation. Double buffering is also used to reduce the overhead of buffer locking. It is shown that the CMB-SMP protocol outperforms a synchronous super-step protocol in terms of the speedups achieved. The paper also discusses the cache behaviour of the CMB-SMP protocol implementation since cache misses are very expensive with today's high clock speed processors. Keywords: virtual factory simulation; wafer fabrication modeling; parallel discrete event simulation
Introduction 1
Parallelising a virtual factory simulation, a plant-wide simulation including the modeling of manufacturing processes, business processes, and communications network, is the major concern of this study. This simulation allows one to model and analyse the behaviour of the system by looking at the overall activities of the system. The simulation results obtained will then be much more accurate and realistic. Due to the anticipated complexity of this detailed modeling, parallel discrete event simulation (PDES) strategies are applied. Our initial focus is on the electronics industry, in particular the wafer fabrication plant, without the modeling of business processes and communications network. This strategy allows us ®rst to exploit parallelism within each model before integrating them to form a single large virtual factory model. When a system is broken down into logical processes (LPs) that can be simulated in parallel, these LPs must not violate the causality constraint. Events must strictly be processed in timestamp order. Many variations of PDES protocols have been proposed in the literature to ensure that the simulation adheres to this constraint. In general, these protocols can be classi®ed into two major classes: conservative2±6 and optimistic.7,8 The conservative protocols allow the simulation to proceed only up to a safe time that avoids any causality error. Th
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