Multiprocessor Systems on Chip Design Space Exploration
In the domain of embedded systems the contradicting requirements of computational performance, energy efficiency and flexibility, together with the shrinking time-to-market and extremely short product lifecycles, exhibits one of the most challenging assig
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Torsten Kempf
•
Gerd Ascheid
•
Rainer Leupers
Multiprocessor Systems on Chip Design Space Exploration
ABC
Torsten Kempf RWTH Aachen University Institute for Integrated Signal Processing Systems (ISS) Sommerfeldstr. 24 52074 Aachen Germany [email protected]
Rainer Leupers RWTH Aachen University Software for Systems on Silicon Templergraben 55 52056 Aachen Germany [email protected]
Gerd Ascheid RWTH Aachen University Institute for Integrated Signal Processing Systems (ISS) Walter-Schottky-Haus Room 24 A 207 Sommerfeldstr. 24 52074 Aachen Germany [email protected]
ISBN 978-1-4419-8152-3 e-ISBN 978-1-4419-8153-0 DOI 10.1007/978-1-4419-8153-0 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2011921340 c Springer Science+Business Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
Dedicated to Meike and Flora, to my brother Tibor and to my parents Brigitte and Wolfgang.
Preface
This book highlights the research conducted in the area of Multi-Processor Systemon-Chip design for more than five years. The work documented within was carried out during my time at the Institute of Integrated Signal Processing Systems (ISS) at the RWTH Aachen University. More than putting forth a brilliant idea, the conducted work reflects a careful evolution of design methodologies and associated tooling. The original motivation dates back to the GRACE++ methodology. This early attempt of system level modeling with SystemC targeted the efficient and convenient exploration of complex architectures, with particular focus on communication architectures. The tight links to industry partners and the ongoing development turned this technology into a commercialized tool called Architects View Framework. At the time I joined the ISS as a researcher, plenty of experience had been gained in modeling System-on-Chip platforms. By the investigation of several industrial platforms, we soon discovered that the detailed modeling of processing elements limited the capabilities of design space exploration. Accordingly, we extended the methodology to a more abstract modeling of processing elements and, furthermore, broadened it to capture the challenges of temporal and spatial task mapping. With the help
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