An Efficient FPGA Architecture for Reconfigurable FFT Processor Incorporating an Integration of an Improved CORDIC and R
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An Efficient FPGA Architecture for Reconfigurable FFT Processor Incorporating an Integration of an Improved CORDIC and Radix-2r Algorithm M. S. Kavitha1 · P. Rangarajan2 Received: 6 November 2019 / Revised: 21 April 2020 / Accepted: 22 April 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract In ultra-high sampling rates, FFT is widely used for acoustic emission signals. In this manuscript, the effectual architecture of hardware is presented based on the execution of FFT due to radix-2 frequency decimation algorithm (R2DIF) and channeled method that allows data to be effectively shared through storage by shift registers. An optimal rotation method/design uses the modified digital coordinate rotation computer algorithm (m-CORDIC) as well as Radix- 2r depending on coding scheme to replace complex multiplier as FFT. The m-CORDIC algorithm enhances computing confluence, while Radix-2r allows the logarithmic reduction of the adder steps. The suggested design does not need large blocks of memory used to maintain the factor as twiddle. Experimental outcomes displays the presented design performs the existing methods by achieving high accuracy and throughput. Compared to the CSD as well as DBNS, novel radix-2r encoding desires an average of 23.12% and 3.07% fewer additions, respectively. The expansion of CSD is canonical signed-digit. Keywords Fast Fourier transform · Radix-2 decimation in frequency (R2DIF) · Coordinate rotation digital computer (CORDIC) algorithm · Canonical signed digit (CSD) · Radix-2r · Multipath delay commutator (MDC)
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M. S. Kavitha [email protected] P. Rangarajan [email protected]
1
Department of Electrical and Electronics Engineering, R.M.K Engineering College, Thiruvallur district, Tamil Nadu, India
2
Department of Electrical and Electronics Engineering, R.M.D. Engineering College, Kavaraipettai, Tamil Nadu, India
Circuits, Systems, and Signal Processing
1 Introduction Digital communication, sensor signal processing and synthetic aperture radar (SAR) are used fast Fourier transform (FFT) as basic algorithm. At real-time communication system, it is always the most time consumption part. Thus, in FFT accelerator, maximum requirements in the effectual of hardware such as size scalable, throughput and flexibility are put as forward [8]. 4G LTE, 5G, Internet of Things (IoT), and so on, are the modern maximum speed signal processing as well as communications standards that necessitate high throughput implementation of FFT [24]. In signal processing, it plays a great rule as, FFT accelerator as well as coordinate rotation digital computer (CORDIC). The twiddle direction prediction present in a configuration floating-point FFT accelerator depend on CORDIC rotation reduces the hardware cost and the memory is saved by the generated twiddle angles. Thus, using a new method consisting of parallel segmented repetition and compressed repetition based on redundant CSA and CORDIC, the latency for every repetition is reduced and then CORDIC rotation is carried out effecti
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