FPGA-Based Reconfigurable Architectures for DSP Computations
With extensive usage of Field Programmable Gate Arrays (FPGAs), a reconfigurable computing platform enhances the wide variety of Digital Signal Processing (DSP) applications using Lookup Table (LUT), Flip-Flop, and multiplexers. Reconfigurable computation
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Abstract With extensive usage of Field Programmable Gate Arrays (FPGAs), a reconfigurable computing platform enhances the wide variety of Digital Signal Processing (DSP) applications using Lookup Table (LUT), Flip-Flop, and multiplexers. Reconfigurable computation using memory becomes a subject of current research. FPGAs can be reprogrammed an unlimited number of times in which various DSP algorithms can be executed on a single hardware device, just as many different software algorithms can run on a conventional processor. The general architectures for DSP consist of a reconfigurable interconnection, Computational Elements (CEs), and memory. This article discusses on the CE architectures based on Memory (CEMs) and Serial arithmetic (CESs). Reconfigurable computing based on memory is much faster, reliable, and, hence the computation using memory requires less delay and power. The CEMs perform multiplication and addition using LUT and the CESs perform computation using serial arithmetic’s. The results of the CESs, CEMs, and the computational reuse processing elements are compared. The architectures design based on CEMs significantly improves the performance of the previously reported results in terms of speed, area, and power using Xilinx Virtex-II FPGA, and Xilinx Vivado software. Keywords FPGA configuration · Computational element architecture · On-Chip memory · DSP specific architecture
J. L. Mazher Iqbal (B) Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Avadi, Chennai, India e-mail: [email protected] T. Manikandan Rajalakshmi Engineering College, Chennai, India e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2021 P. Suresh et al. (eds.), Advances in Smart System Technologies, Advances in Intelligent Systems and Computing 1163, https://doi.org/10.1007/978-981-15-5029-4_48
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J.L. Mazher Iqbal and T. Manikandan
1 Introduction Nowadays, consumer appliances are considerably progressive. Consumer appliances are more functional and portable. The important issues in developing Very Large Scale Integrated Circuit (VLSI) architectures for communication systems and Digital Signal Processing (DSP) applications are power, speed, area, and cost [1]. The key devices to resolve these problems are microprocessors, microcontrollers, DSPs, and Field Programmable Gate Array (FPGAs). There are various methods in conventional computing for the execution of the DSP algorithm, Application Specific Integrated Circuit (ASIC), Microprocessors, and FPGAs [1]. ASICs are very efficient and fast because they are designed to perform a specific computation, but it is not possible to alter the circuit after fabrication. As the need for complex compilation for DSP surges, reconfigurable computing remains an active area of research. Many DSP operations for various DSP applications are implemented using enormous logic blocks present in FPGA. Reconfigurable computing using FPGAs outperforms the DSP processor and microprocessor in terms of performance, massive parallel
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