An Experimental Technique to Obtain the Specific Contact Resistance of Multi-Layer Interconnections
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H.B.
HARRISON , G.K.
REEVES
and A.J. WALTON
IBM Thomas J. Watson Research Centre, Yorktown Heights, New York, U.S.A. on leave from R.M.I.T. Australia. ** Telecom Australia Research Laboratories, Clayton, Australia. *** Edinburgh Microfabrication Facility, University of Edinburgh, Scotland, U.K. *
ABSTRACT The specific contact resistance between any two interconnecting layers is of vital importance in determining the total interconnection resistance of these layers. We present here an experimental technique to obtain the specific contact resistance when both of the conducting layers have finite conductivities of similar magnitudes. This structure is then used to obtain practical information on the poly to single crystal interconnection system, details of which are present. Finally a modification to this system is proposed and its status reviewed.
INTRODUCTION In this letter we use previously published generalized theory [1] based on a two port distributed network to develop a test structure suitable for assessing interfaces between interconnecting layers in integrated circuits. In particular the structure is used to obtain the specific contact resistance between interconnecting layers, a parameter that strongly influences the contact resistance found in integrated circuits. As geometrical feature size decrease, parastic contact resistance can become an important factor in limiting circuit performance. The test structure also provides information on the sheet resistances of the interconnecting layers within the contact area. This test structure has been used to assess the poly to single crystal interface in buried contact nMOS technology. We report here theoretical and practical considerations for the use of the structure along with measured data obtained from it. We also include a modification to this structure that is the subject of current practical investigation. THE ELECTRICAL TEST STRUCTURE The distributed electrical network representing the contact interface is shown in Figure 1. The sheet resistances of the layers within the contact region are represented by R' SP (poly layer) and RSK (single crystal layer), the contact has a width W, length d and a specific contact resistance 2). For this model we have shown [1) that the standard contact Pc. (-cm resistance, current flow in at node A and out from node C, with the voltage taken from A to C is given by
VAC R'SpRSK d 1 I = R'Sp + RSK W + aW(RSK + Rsp)
Mat. Res. Soc. Symp. Proc. Vol. 54.
2R'SpRSK sinh a
2
1986 Materials Research Society
p )cothadl (P
788
where
(2)
a= a (RsK +'s)/p + R'SP)/pcj 1/2.
POLYSIUCON LAYER (Rsp) PC
A
*C
D
SINGLE CRYSTAL SIUCON (Rsk) Figure 1
Electrical model for the contact interface.
enters node A and exists from node A folded contact resistance where current D, with the voltage taken across these two nodes is also defined and given as: VAD I
F
RSK + R'sp coshad aW
(3)
the above equations to be found an To enable the various parameters in electrical test structure of the form shown in Figure 2 was devised for
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