An Improved Analytical Model of Outer Fringe Capacitance of Multifin Diamond Shaped Raised Source/Drain FinFET
- PDF / 2,964,514 Bytes
- 14 Pages / 595.224 x 790.955 pts Page_size
- 91 Downloads / 185 Views
ORIGINAL PAPER
An Improved Analytical Model of Outer Fringe Capacitance of Multifin Diamond Shaped Raised Source/Drain FinFET Savitesh Madhulika Sharma1
· S. Dasgupta2 · M. V. Kartikeyan2
Received: 31 January 2020 / Accepted: 1 September 2020 © Springer Nature B.V. 2020
Abstract Recent studies have pointed out that FinFET are immune to short channel effects (SCEs) but their performances at high frequencies are compromised due to strong fringing field between gate and source/drain region. Because of technological advancement, the gate structure of MOSFET has been improved from planar to nonplanar with an enhancement in the number of controlling gates. In this paper we propose FinFET structure for high frequency applications. The proposed model has been verified with finite element numerical simulations as well as with reported experimental measurements. In this paper, we propose for the first time an analytical model of Outer Fringe Capacitance of Multifin Diamond Shaped Raised Source/Drain FinFET. The development of parasitic model is necessary for accurate quantitative prediction of the parasitics introduced by each part of the device structure. The relative contribution of the total parasitic capacitance is addressed as well as their impact on RF-figure of merit (RF-FOM) (cut-off frequency fT ) is presented. This work presents the possibility to improve fT by about 42% due to reduced parasitic gate capacitance that results from faceted surfaces of S/D region. Keywords FinFET · Multigate transistor · MOSFET · TCAD · Multifin · Multifinger · Fringe capacitance · Parasitic capacitance
1 Introduction Multigate MOSFETs have paved the way to successful development of nanoscale devices and circuits for semiconductor industry without enhanced short channel effects (SCEs). Consequently, more opportunities can be explored further for ensuing ITRS roadmap. Challenges of perpetual scaling and improved speed in nonplanar MOSFETs era are (1) threshold voltage adjustment, (2) fringing capacitance between gate and top/bottom of source drain electrodes, (3) Parasitic resistances and (4) variability. Recent developments in FinFETs are hampered by extrinsic parasitics [1] which are introduced at high frequencies. Investigations of parasitic are critical for digital as well analogue circuit design. To establish a perspective of individual contributions of each region of device in parasitics, many models
Savitesh Madhulika Sharma
[email protected] 1
Dept. of ECE, DVR & Dr. HS MIC College of Technology, Vijayawada, Andhra Pradesh, India
2
Dept. of ECE, IIT, Roorkee, India
[2–9] have been developed. Wu model [10] did not take into account raised source/drain (S/D) structure and the presence of metal contacts and its accuracy is dependent on the four geometry independent constant parameters. For FinFET, ON current (ION ) is increased by increasing the number of fins which in turns enhances the capacitance and resistance of the device. However, multifin configuration for gaining current and power makes difficult relations
Data Loading...
