An Incremental Verification Paradigm for Embedded Systems
Embedded Systems complexity is enhancing many folds in most of the product domains. Changing requirements and uncertainty during early stages of development are of greatest concern for the developing community, as they enhance system development complexit
- PDF / 612,493 Bytes
- 10 Pages / 439.37 x 666.142 pts Page_size
- 34 Downloads / 237 Views
Abstract. Embedded Systems complexity is enhancing many folds in most of the product domains. Changing requirements and uncertainty during early stages of development are of greatest concern for the developing community, as they enhance system development complexities. Verification encompasses all aspects of system development process. This paper proposes an incremental paradigm that incorporates early integration and reduces uncertainty during initial phases of development under changing conditions of requirements. The method can be represented by a cascaded V-model. The verification methodology implementation issues are presented. Keywords: Embedded systems Changing requirements Uncertainty in development Verification method Early integration Division of design-verification-cycle Cascaded V-model Implementation of verification method
1 Introduction Complex embedded systems (CES) have mission critical requirements like real-time and high-confidence performance; accommodate frequent changes in requirements, environment, and technology; large embedded software running on different embedded computing platforms; etc. Examples are robots, modern cars, airplanes, radars, sonar’s, missiles, etc., [1–8]. At present ES are being researched in all aspects and in all phases of development. From requirements uncertainty [1, 2], to system design [3], to Verification and Validation [6–8] to the requirement of new approaches/theories [9], all are being focused by the embedded community. Verification and validation (V and V) activities are associated with all stage of the product lifecycle and account for a substantial share of project budgets, both time and money. Strictly, V and V Stringent market and economic considerations are forcing all concerned into reducing V and V process deficiencies [10] and introducing design methodologies with dedicated resources for important phases of development [5, 11]. All these efforts are directed towards reducing overall cost or to meet market deadlines or to improve performance. This paper focus is design/implementation verification of CES-product under development.
© Springer Nature Singapore Pte Ltd. 2017 M. Singh et al. (Eds.): ICACDS 2016, CCIS 721, pp. 40–49, 2017. DOI: 10.1007/978-981-10-5427-3_5
An Incremental Verification Paradigm for Embedded Systems
41
2 Related Work The verification and validation methodologies reported so far can be categorized into (a) language dependent [3, 6], (b) specific tool (development framework) [4–6], and also commercially available tools [8]. But these tools are not available in all application areas, very expensive (if available), not qualified and also are not easily accessible. Most tools do not cater to incomplete requirements. Such solutions are not easily accessible to the embedded community. As such general method for ‘ES verification and validation’ is required which is useful to the development community. A frame work for re-verification of component-based software systems [5] after modifications of components is presented. The tool supporte
Data Loading...
