Analysis of DLL Jitter due to Voltage-Controlled Delay Line
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Analysis of DLL Jitter due to Voltage-Controlled Delay Line Mohammad Gholami · Gholamreza Ardeshir
Received: 7 September 2012 / Revised: 18 March 2013 © Springer Science+Business Media New York 2013
Abstract In this paper we analyze jitter in a delay-locked loop (DLL) due to uncertainties in the voltage-controlled delay line (VCDL). To obtain a closed-form equation for jitter in the DLL, time-domain equations of the DLL are used. The jitter at the intermediate stages of the VCDL and the jitter of a conventional delay cell are analyzed. The simulation results show that the jitter of the DLL due to mismatch of the delay cells is zero at the beginning and end of the VCDL and is highest at the middle of the VCDL. Also, a DLL is designed in TSMC 0.18 µm CMOS technology to show the accuracy of the proposed analytical method. Keywords DLL · Delay-locked loop · Jitter · Variance · Expected value
1 Introduction Nowadays delay-locked loops (DLLs) and phase-locked loops (PLLs) are widely used in clock generation circuits [5, 11], clock deskewing [3, 16], clock buffers [2], clock synchronization [12] transceivers [4], DRAM [22], SRAM [10], and frequency synthesizers [7, 8]. Jitter is a very small and random deviation in signals caused by mismatches, noise, and inappropriate input signals. For example, jitter is defined as undesired deviation from true periodicity of a signal with respect to a clock reference
M. Gholami is now part of Micro-Electronic Research Group in Babol University of Technology, Babol, Iran. Since 1994, G. Ardeshir has been a member of Electrical Engineering Faculty at Babol University of Technology. M. Gholami () · G. Ardeshir Electrical Engineering Department, Babol University of Technology, Babol, Iran e-mail: [email protected] G. Ardeshir e-mail: [email protected]
Circuits Syst Signal Process
Fig. 1 Structure of conventional DLL
[13, 18]. Jitter may be observed in characteristics such as the frequency of successive pulses, signal amplitude, or the phase of periodic signals [20, 21]. Generally, analog DLLs have better jitter performance compared to digital DLLs [1, 5], and DLLs have lower jitter with respect to PLLs [17]. In this paper the DLL jitter due to uncertainties in the VCDL is analyzed, as well as the jitter of delay cells resulting from mismatch and noise. This paper is organized as follows. Section 2 describes a conventional DLL and its sources of jitter. The time-domain equations of a conventional DLL will be explained in Sect. 3, and Sect. 4 describes DLL jitter due to noisy delay cells. Jitter of a conventional delay cell caused by noise and mismatches in the cell will be explained in Sect. 5. The simulation and results are reported in Sect. 6. 2 Conventional Delay-Locked Loops Figure 1 shows the structure of a conventional DLL. The conventional DLL consists of a phase-frequency detector (PFD), charge pump (CP), loop filter (LF) and a voltage-controlled delay line (VCDL). In the DLL, REF, the reference clock, passes through the VCDL. Then the phase of the output signal, OUT, i
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