Analytical modelling of a Cyl-JLAM MOSFET in the subthreshold region using distinct device geometry
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Analytical modelling of a Cyl‑JLAM MOSFET in the subthreshold region using distinct device geometry Sarita Misra1 · Sudhansu Mohan Biswal2 · Biswajit Baral2 · Sanjit Kumar Swain2 · Angsuman Sarkar3 · Sudhansu Kumar Pati2 Received: 21 March 2020 / Accepted: 28 July 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract As short-channel effects (SCEs) are a major issue in the nanoscale regime, investigation of the subthreshold behaviour of nanometer-scale devices is critical. Here, we have developed an analytical model for a cylindrical gate junctionless accumulation-mode MOSFET (Cyl-JLAM MOSFET) to analyse its behaviour in the subthreshold region. The two-dimensional Poisson equation is solved to develop the analytical model by approximating the potential profile along the channel to be parabolic. We have formulated the expression for potential at the centre and electric field along the channel from the developed model. The key performance factors of SCEs including threshold voltage (VTH) roll-off, drain-induced barrier lowering and subthreshold slope are explored with respect to the geometry of the device parameters, i.e. body thickness of the cylindrical silicon pillar, length of the channel and thickness of the oxide layer. The results of our model are in good agreement with numerical simulations. The TCAD ATLAS 3D device simulator accounts for all the physical models required during the simulation. In this paper, the simple and distinctly formulated analytical model supports the application of the Cyl-JLAM MOSFET in integrated circuit design and optimization. Keywords Cylindrical gate · Junctionless · Accumulation mode · Centre potential · Threshold voltage roll-off · DIBL · Subthreshold slope
1 Introduction Short-channel effects are a major obstacle in the path towards downscaling of traditional bulk Si metal–oxide–semiconductor field-effect transistors (MOSFETs) to the nanoscale regime. To circumvent this problem while maintaining the enhanced performance of complementary metal–oxide–semiconductor (CMOS) devices, new technologies must be incorporated, as suggested by the International Technology Roadmap for Semiconductors (ITRS) [1]. Increased leakage current and degradation of the ION/IOFF ratio occur due to the increase in the drain-induced barrier lowering * Sarita Misra [email protected] 1
Gandhi Institute of Technological Advancement (GITA), Bhubaneswar, Odisha 752054, India
2
Silicon Institute of Technology, Bhubaneswar, Odisha 751024, India
3
Kalyani Government Engineering College, Kalyani, West Bengal 741235, India
(DIBL) and threshold voltage roll-off, which are two main manifestations of SCEs. With the advancements in fabrication technology, multigate FETs (MUGFETs) will replace conventional MOSFETs [2–4]. The SCEs are reduced in MUGFETs in comparison with conventional devices, as the channel is better controlled by gates. The gate control capability of the cylindrical structure is increased by wrapping the gate around the channel in a surrounde
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