A New SiGeC Vertical MOSFET: Single-device CMOS (SD-CMOS)
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1252-I02-10
A new SiGeC Vertical MOSFET: Single-Device CMOS (SD-CMOS) Carlos J. R. P. Augusto and Lynn Forester Quantum Semiconductor LLC, 4320 Stevens Creek Blvd., Suite 212, San Jose, CA 95129, U.S.A. ABSTRACT A new type of silicon-based Vertical MOSFET concept is presented, Single-Device CMOS (SD-CMOS), in which the same structure can be operated as NFET or as PFET, depending on the biasing conditions [1,2]. SD-CMOS offers new possibilities for simpler CMOS integration schemes; one of them requiring only 4 masks for the “Front-End”; with less cost to manufacture than any integration scheme requiring the fabrication of two devices with opposite doping polarities. Numerical simulations with a commercial device simulator [3] confirm the validity of the concept and demonstrate its feasibility for scaling to 10nm channel lengths. INTRODUCTION V-MOSFETs made by epitaxial growth can easily have channel lengths smaller than 10nm (LCh0, and operates as a PMOSFET when VDS
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