ASIC/SoC Functional Design Verification A Comprehensive Guide to Tec
This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon The author outlines a
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ASIC/SoC Functional Design Verification A Comprehensive Guide to Technologies and Methodologies
ASIC/SoC Functional Design Verification
Ashok B. Mehta
ASIC/SoC Functional Design Verification A Comprehensive Guide to Technologies and Methodologies
Ashok B. Mehta Los Gatos, California USA
ISBN 978-3-319-59417-0 ISBN 978-3-319-59418-7 (eBook) DOI 10.1007/978-3-319-59418-7 Library of Congress Control Number: 2017941514 © Springer International Publishing AG 2018 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. Printed on acid-free paper This Springer imprint is published by Springer Nature The registered company is Springer International Publishing AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland
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To My dear wife Ashraf Zahedi and My dear parents Rukshmani and Babubhai Mehta
Preface
Having been a design and verification engineer of CPUs and SoCs for over 20 years, I’ve come to realize that the design verification field is very exhaustive in its breadth and depth. Knowing only SystemVerilog and UVM may not suffice. Sure, you need to know UVM (Universal Verification Methodology) but also SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CRV (constrained random verification), CDC (clock domain crossing) verification, interconnect NoC (Network on Chip) verification, AMS (analog/mixed signal) verification, low-power verification (UPF), hardware acceleration and emulation, hardware/software co-verification, and static formal (aka static functional aka formal property check) verification technologies and methodologies. I noticed that there isn’t a book that gives a good overview (high level but with sufficient detail) of the technologies and methodologies at hand. Engineers rely on white papers, blogs, and EDA vendor literature to get some understanding of many of these topics. That was the impetus f
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