Capacitance Measurement Technique for Determining the Out-of-Plane Coefficient of Thermal Expansion for Low-k Dielectric
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B8.14.1
Capacitance Measurement Technique for Determining the Out-of-Plane Coefficient of Thermal Expansion for Low-k Dielectrics Swarnal Borthakur1, 2, Andreas Knorr1, 3, Paul S. Ho2, Wen-Li Wu4 SEMATECH1, The University of Texas at Austin 2, Infineon Technologies3, NIST4 SEMATECH, 2706 Montopolis Drive Austin, TX 78741, USA ABSTRACT The out-of-plane coefficient of thermal expansion (CTE) is experimentally determined from capacitance measurements. This technique relies on accurate capacitance measurements over temperature in a N2 environment. The CTE values obtained are higher than those obtained from the X-ray reflectivity (XRR) method. The higher CTE values are believed to be due to the dependence of the dielectric constant on temperature. This technique can validate the XRR method and can be useful for comparing different materials. It is relatively easier to perform and simpler than the XRR technique. INTRODUCTION As scaling approaches nanometer levels the RC delay of interconnects has become a dominant factor in determining the total delay. The low-k dielectrics that are being investigated for reducing the capacitance are porous carbon-doped oxide or are porous organic materials. A major concern in the integration of low-k materials is the thermal stress generated in the structure due to the thermal expansion mismatch between the lowk material and its adjacent surroundings. The CTE can be determined from capacitance measurements [1][2]. The CTE is given by equation (1). (L-Lo) / Lo = α (T-To)
(1)
Where (L- Lo) is the change in dielectric thickness, (T-To) is the temperature range and α is the CTE. The capacitance of a parallel plate capacitor is given by equation (2). C=εoεrA/L
(2)
Where C is the capacitance, A is the area, L is the dielectric thickness, εo is the permittivity of vacuum (8.854x10-12 Fm-1) and εr is the relative permittivity or the k value. Combining equations 1 and 2 and assuming that the area is constant, we get equation 3. α =[(εr/C-εro/Co)/(εro/Co)]/[T-To]
(3)
B8.14.2
In an aluminum dot MIM capacitor with a silicon substrate, the dielectric is confined by the substrate [3][4]. The substrate confinement causes a constraint and increases the deformation along the vertical direction. This contributes to the total out-of-plane CTE. The actual CTE is given by equation 4 assuming that the Poisson’s ratio is same in both directions (γ13= γ12 = γ ). α actual = [(1- γ)/(1+ γ)] α measured + [2 γ /(1+ γ)] α substrate
(4)
Assuming the Poisson’s ratio is 0.3 and α substrate of Si is 2.6 ppm/oC we get, α actual = 0.54 α measured + 1.2 ppm/oC Therefore, the actual CTE is approximately half the measured CTE. In this paper we present a characterization technique for determining the out-of-plane CTE of low-k materials from capacitance measurements. The values obtained by this technique will be compared with the values obtained by the XRR technique [5], which also measures the out-of-plane CTE. The discrepancy between the measurements and the limitations of this technique will be discussed.
EXPERI
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