Carrier Transport and Lateral Conductivity in Nanocrystalline Silicon Layers
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Carrier Transport and Lateral Conductivity in Nanocrystalline Silicon Layers H. B. Kim, L. Montes, R. Krishnan, P. M. Fauchet, and L. Tsybeskov Nanoscale Silicon Research Initiative, Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, U.S.A ABSTRACT We have studied carrier transport and lateral electrical properties of nanocrystalline Si layers containing size controlled Si nanocrystals. Using results from direct current (dc) and alternating current (ac) conductivity measurements, the charging of Si nanocrystals and Coulomb blockade effect are discussed. INTRODUCTION Low-dimensional Si/SiO2 based structures have attracted strong attention due to their interesting physical properties and potential applications in nanoscale electronic devices [1-4]. Previous work on carrier transport in layered structures with alternating layers of nanocrystalline Si and amorphous, tunnel transparent SiO2 has focused on vertical (i.e., perpendicular to layers) conductivity [5-7]. However, the application of these structures in ultra-high density memory requires an understanding of "cross talk" between Si nanocrystals and lateral carrier transport within the nanocrystalline Si (nc-Si) layer. The lateral carrier transport can be studied using dc and ac lateral electrical conductivity in thin layers containing size-controlled Si nanocrystals. In this paper, we present such studies and discuss important conclusions with a focus on the advantages and limitations of our fabrication and measurement techniques. SAMPLE FABRICATION A 100 nm-thick SiO2 layer was grown by dry oxidation at 1100 oC on a (100) n-type, 5~10 Ohm cm Si substrate. This layer was used to block direct charge transfer between the layer containing Si nanocrystals and Si substrate. Several samples with a-Si layer thickness ranging from 3 nm to 10 nm were deposited on top of the SiO2 layers by radio frequency magnetron sputtering. The samples were annealed by rapid thermal annealing (RTA) to nucleate Si nanocrystals within the sputtered a-Si layer [8, 9]. To measure lateral conductivity of this layer, top Al electrodes with an area of 10 mm2 and lateral spacing of ~ 200 µm were deposited by thermal evaporation. Electrical measurements were carried out at room temperature using a HP 4274A LCR meter and a Keithly 595 quasistatic capacitance-voltage meter. EXPERIMENTAL RESULTS Figure 1 shows a schematic diagram of the sample structure. The diameter of Si nanocrystals is almost equal to the thickness of the sputtered a-Si layer [5, 8] and their shape is approximately spherical due to competition between surface and volume tension [10].
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Al Gate
SiO2
c-Si
Figure 1. A schematic diagram of a sample structure. The layer containing Si nanocrystals is on a 100 nm thick, thermally grown SiO2 layer. Silicon nanocrystals are formed within a-Si layer by rapid thermal annealing with vertical size close to the thickness of initially a-Si layer [5,8]. Two top lateral Al gate electrodes are used to measure the lateral sample conductivit
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