Carrier Transport in Polycrystalline and Amorphous Silicon Thin Film Transistors
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vacuum. In order to have a smooth surface by taking out slowly hydrogen from a film, irradiation with multi energy steps was performed [13]. The laser energy was controlled up to 230 mJ/cm 2 , which is just below the amorphization threshold (240 mJ/cm 2 ) for 20-nm-thick films. The laser heating cause diffusion of doapnt atoms with a diffusion length at most 60nm [14]. The dopant atoms therefore diffuse vertically through the whole thickness of Si layers, but they did not shorten the channel length significantly. After the irradiation, the silicon layers were hydrogenated using hydrogen plasma with 5 W for 30 sec. at 270 °C in order to reduce defect states [10]. In order to form a SiO2 gate insulator layer at a low temperature with low damage, two technologies have been developed. One is a triode type remote plasma CVD [8-10] and the other is SiO evaporation with an oxygen ambient [11,12]. The remote-plasma-CVD equipment has mesh electrodes between the top electrode and the substrate in order to confine the plasma between the top electrode and meshes and keep it away from the substrate. Mixed gases with oxygen and helium were introduced and their plasma was generated by applying RF voltage to the top electrode. The langmiur analysis with dependence of current on voltage applied at the meshes revealed that the electron density was lower than 104 cm- 3 in the region between the meshes and the substrate, while the electron density was higher than 109 cm-3 in plasma above the meshes [9]. The oxygen and helium radicals come down in a lower part through the holes in the meshes and decompose SiH4 gas which was flowed below the meshes. A Si02 film was consequently formed on a substrate heated at 270 oC. The deposition rate was 6nm/min at RF power (13.56 MHz) of 5W. The breakdown voltage was 4.5 MV/cm. The investigation of the Al-gate-metaloxide-silicon (MOS) capacitor using single crystalline silicon revealed that the minimum interface trap density was 2x1l0U cm-2 eV- 1 using the method of a H20 vapor annealing at 270 oC for one hour, which Sano et.al. has recently developed [15]. On the other hand, the interface trap density for a MOS capacitor fabricated using conventional plasma CVD without any mesh was 7x10 11 cm- 2 eV- 1 even after the H20 vapor annealing because of serious plasma damage, which the annealing can not remove. SiO evaporation with an oxygen atmosphere was also used for forming the gate insulator. A powder of SiO was evaporated by heating the Ta boat with an oxygen flow. Hot molecular SiO evaporated from heated SiO powders effectively react with oxygen gas and SiO2 films was formed on substrates at room temperature. The deposition rate was controlled 8 nm/min. The deposited film can have a large amount of oxide charge caused by E' centers (dangling bond of Si in Si0 2 ) especially for the deposition condition of a lower oxygen flow rate. The density of the oxide charge is reduced to as small as 8x10 9 cm- 2 by increasing oxygen flow rate to 2.5 Sccm during deposition [16]. The minimum interface trapping
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