Characterization of 4H-SiC MOS Capacitors by a Fast-Ramp Response Technique
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Mat. Res. Soc. Symp. Proc. Vol. 423 01996 Materials Research Society
for Deep Depletion Measurements
Fig. 1: Experimental set-up for fast-ramp response measurements on MOS capacitors. The experimental system consists of a high voltage ramp generator which is capable of providing a negative voltage pulse ranging from 10 V to 10 kV, at variable slopes from 10 V/ms to 100 V/ms and pulse duration in the range of 0.ims to 100 ms. Since the ramp generator is designed with independent control over the slope as well as the pulse duration, it is possible to study the variation in the MOS electrical characteristics as a function of either of the above parameters. The experimental sequence for the characterization of MOS structures performed in the present case involves the application of a fixed slope pulse with varying pulse duration so that the peak applied voltage increases with increasing pulse duration. The slope of the ramp voltage is chosen such that it is rapid enough to avoid any thermal generation in the semiconductor. The MOS capacitor structures used in the present experiments were fabricated on n-type research grade 4H - SiC substrates with - l018 cm-3 doping concentration and a 5gtm epilayer of 3 _ 105 to 1016 cm concentration. A thermal oxide of 1200A - 1800A thickness was grown on top of the epilayer by wet oxidation at 1150'C in a quartz furnace. Al gate contacts of different diameters (0.1mm to 1.0 mm) were defined on the oxide layer by photolithography. All the MOS structures were at first characterized using room-temperature high frequency C-V measurements at 100 kHz under perfect dark condition. The MOS structures were then tested using the ramp response technique, first in the accumulation mode and then in the deep depletion mode. As indicated in Fig. 1, for the accumulation measurements the negative high voltage pulse is applied to the bottom ohmic contact of the capacitor (for the n-type semiconductor), while the Al gate is connected to the ground via a Wk2 current viewing resistor (CVR). In this circuit configuration the applied voltage appears entirely across the oxide layer, and hence the characteristics of the oxide layer can be determined. Since the applied ramp voltage has a constant slope (dV/dt), for a fixed oxide capacitance (Co,), the measured current should be ideally a constant value corresponding to the displacement current (CoxdV/dt). In case of a poor quality oxide, with significant leakage current, an additional conduction current proportional to the oxide conductivity will be superimposed on the measured displacement current. Hence by comparing the measured total current with the theoretical displacement current that is expected (since C0 x is known from the C-V measurements), the oxide conductivity for poor quality oxides can be determined. The MOS structures with no leakage through the oxide were further tested in the deep depletion mode. In this configuration, as shown in Fig. 1, the negative ramp voltage is applied to the gate of the MOS structure in series with a fixed pos
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