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C9.8.1/E9.8.1

Characterization of Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) FETs Using (Sr,Sm)0.8Bi2.2Ta2O9 (SSBT) Thin Films Hirokazu Saiki1 and Eisuke Tokumitsu1,2 1 Precision and Intelligence Laboratory, Tokyo Institute of Technology 4259 Nagatsuta, Midori-ku, Yokohama, 226-8503, Japan 2 IT-21 Center, Research Institute of Electrical Communication, Tohoku University 2-1-1 Katahira, Aoba-ku, Sendai, 980-8577, Japan

ABSTRACT We have fabricated and characterized Pt (60nm) / (Sr,Sm)0.8Bi2.2Ta2O9 (SSBT, 130nm) / Pt (60nm) / Ti (10nm) / SiO2 (10nm) / p-Si (MFMIS:metal-ferroelectric-metal-insulatorsemiconductor) structure FETs. The area ratio, the ratio of SSBT capacitor area to SiO2 capacitor, is varied from 1 to 15 in the MFMIS-FETs. It is demonstrated that MFMIS-FETs with area ratio of 6 have memory window of 0.5V with supply voltage of 5V. Dependence of memory window on the area ratio is discussed.

INTRODUCTION Ferroelectric random access memory (FeRAM) [1-9] is a promising memory device because it has many advantages such as nonvolatile, high speed operation, and low power consumption. Generally speaking, we can classify FeRAMs into 2 types, i.e. “capacitor-type” and “transistor-type”. The “capacitor-type” FeRAMs are now commercialized. On the other hand, the “transistor-type” FeRAMs are superior to the “capacitor-type” FeRAMs because they have merits such as non-destructive readout and small cell size. It should be noted that the required characteristics of ferroelectric films are quite different in each type of FeRAMs. For the “capacitor-type” FeRAMs, large remanent polarization (Pr), large Pr/Ps ratio (Ps means saturation polarization), and small coercive field (Ec) are required for ferroelectric films because such characteristics result in large readout current, large on/off ratio, and low operation voltage, respectively. On the other hand, for the “transistor-type” FeRAMs, small polarization (both Pr and Ps) and relatively large Ec are required for ferroelectric films. The former is needed to match the polarization with the charge which controls channel conductivity of Si MOSFETs, and the charge amount is only about 1µC/cm2. The latter is needed to obtain a certain memory window, which is given by twice of the products of Ec and the thickness of the ferroelectric film. For example, a ferroelectric film with Ec of 100kV/cm and thickness of 100nm products a memory window of 2V. The Pr values of conventional ferroelectric films are much larger than 1µC/cm2. To overcome this “charge mismatch” problem, we use metal-ferroelectric-metal-insulatorsemiconductor (MFMIS) structure because we can design MFM capacitor area (SF) and MIS structure area (SI) independently [8,9]. We previously reported that the area ratio, SI/SF, of MFMIS-FETs using conventional ferroelectric films should be larger than 10 to obtain stable memory operation, because of “charge-mismatch” problem. However, large area ratio needs large device size and makes it difficult to realize high-density integration. Hence, small area rati