Characterization of MFMIS and MFIS Structures for Non-volatile Memory Applications
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D3.2.1
Characterization of MFMIS and MFIS Structures for Non-volatile Memory Applications Mosiur Rahman, T. S. Kalkur and Shunming Sun University of Colorado at Colorado Springs, Colorado Springs, 80933-7150, USA Fred P. Gnadinger, David Dalton, Daesig Kim, Viorel Olariu and David Klingensmith COVA Technologies Inc., Colorado Springs, CO 80906 USA;
ABSTRACT To eliminate the interface reaction problems between ferroelectric and semiconductor in MFS (metal-ferroelectric-semiconductor) as well as ferroelectric and insulator in MFIS (metal-ferroelectric-insulator-semiconductor) structures, a gate layer sandwich of the MFMIS (metal-ferroelectric-metal-insulator-semiconductor) is proposed. This structure consists of Pt-SBT-Pt-ZrO2-SiO2-Si stacks. In the MFMIS structure the MIS capacitor is separated from the ferroelectric MFM capacitor through a metal as a floating gate. Therefore, the MIS capacitor with SiO2 and ZrO2 as an insulator with excellent interface properties can be used and MFM acts as an ideal ferroelectric capacitor. As MFMIS is a series combination of MFM and MIS capacitors, it behaves as a voltage divider. The gate voltage is divided according to the capacitance ratio of the MIS and MFM structures. Since the fabricated devices have access to the floating gate, characteristics of the MFM and MIS capacitors can be determined independently to compare the characteristics of the MFMIS structure as a single capacitor. The ferroelectric can be programmed in one direction and the field effect due to that can be analyzed. The MFMIS structures showed significant memory window due to the polarization of ferroelectric thin films but the retention time was short. The short retention time was due to the depolarization field being larger than coercive field of the ferroelectric thin film. INTRODUCTION The bi-stable hysteresis characteristic of a ferroelectric material is suitable for developing non-volatile data storage devices [1,2]. The principle of a ferroelectric gate field effect transistor (FeFET) is based on a conventional Si MOSFET (Metal Oxide Semiconductor Field Effect Transistor) whose gate dielectric is a ferroelectric material, or a stack of dielectrics with a ferroelectric layer [1,2]. The application of a voltage pulse to the gate sets the direction of the polarization, and hence the value of the drain current of the transistor.
D3.2.2
Control Gate (G2) Floating Gate (G1)
Metal Ferroelectric Source (S)
Metal Insulator
Drain (D)
Semiconductor
Bulk (B) Figure 1 Structure of MFMIS Transistor The simplest of FeFETs is MFS which is based on a stack composed of a metal gate electrode, a ferroelectric, and the semiconductor. To develop a working MFS FET, it is necessary that the lattice mismatch between Si and the ferroelectric should be as small as possible and the number of interface states (traps) should be less than 1012 eV-1 cm-2 [2,3]. With the conventional well known ferroelectric thin films such as lead zirconate titanate (PZT) and strontium bismuth tantalite, it is difficult to attain low interf
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