Process Integration for Nonvolatile Ferroelectric Memory Fabrication
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MRS BULLETIN/JUNE 1996
plate line between Vo and 0 V. To read the capacitors along a row, the word line turns on the access transistors, and the plate line is pulsed. A greater displacement current occurs for the capacitors previously in a logic "1" state than for those in a logic "0" state. A sense amplifier compares the bit capacitor against a reference capacitor to identify the logic state. The latching operation of the sense amplifier then drives the bit line voltage to Vo for a logic "1" and to 0 for a logic "0." A plate line transition then rewrites the previously stored data. This operation is for a destructive read memory. Various nondestructive read operations for ferroelectric capacitors are under investigation and exploit some asymmetry of electrical
behavior or asymmetry of operation. While a nondestructive read is generally desirable, there are additional issues with a reduced signal difference between the two logic states and with the potential for the read operation to disturb the ferroelectric polarization. However, the process integration generally will be similar for either type of read operation. FeRAMs enjoy substantial advantages over the usual nonvolatile memories such as the floating gate electrically erasable, programmable read-only memory (EEPROM) and flash EEPROM. The floating gate technologies use electron tunneling to store charge on an isolated transistor gate that requires high voltages (12-18 V) and relatively long write times (~1 ms). In contrast, FeRAMs have a fast write speed ( = 100 ns) and operate at standard supply voltages (=£5 V ). Also the floating gate memories require a separate erase operation whereas the FeRAMs use a direct overwrite of prior data. The major challenge in achieving widespread commercialization of FeRAMs is the integration of ferroelectric capacitors with the complementary metal oxide semiconductor (CMOS) technology.3"5 This requires formation of millions of micronor submicron-scale capacitors with uniformly good properties on each silicon wafer. Additionally, numerous material and process interactions must be addressed so that the ferroelectric capacitor formation does not damage the CMOS transistors, and subsequent integration processes do not damage the ferroelectric properties. These challenges are the topic of this article.
Hysteresis Loop
Ferroelectric Capacitor
WRITE "0"
WRITE "1"
READ/WRITE
Figure 1. Ferroelectric nonvolatile memory array and typical timing diagram.
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Process Integration for Nonvolatile Ferroelectric Memory Fabrication
Integration Architecture Typical integration schemes for FeRAMs are illustrated in Figure 2. The ferroelectric capacitors are formed over an interlevel dielectric (ILD) covering the completed silicon transistors but beneath the interconnect metallization. This is a logical location since the ferroelectric crystallization temperatures (550-800°C) generally are lower than the transistor process temperatures but higher than the interconnection process temperatures. The triple-tier capacitor of Figure 2a requ
