CMP Revisited for the MEMS/Foundry Era
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CMP Revisited for the MEMS/Foundry Era Lawrence Camilletti, Jazz Semiconductor, Newport Beach, CA ABSTRACT
Business/foundry driven requirements have necessitated the creation of modified ILD CMP processes for terminal metal-die planarization for BiCMOS SOC/MEMS applications. Therefore, despite much CMP process evolution, this paper ‘steps-back’ to test CMP assumptions first introduced within ILD process norms on these new applications at 10X typical process topographies. Evaluation of planarization targets, density effects, oxide budgets, as well as associated integration, throughput and metrology considerations within this expanded regime are discussed. ANOVA on inter- and intra-die (WIWNU and WIDNU) variation are used to quantify results throughout the work. INTRODUCTION
Application of ILD CMP processes for die/terminal metal (MT) planarization has been introduced due to topographical and depth of field requirements of post fab processing. However, when integrated within a fab with modularized process flows, ILD CMP processing at these layers requires the planarization of far more ambitious topographies than found at conventional ILD layers. Further, the lack of dummification at terminal metal to ease packaging and minimize upper level inductor coupling further skews nominal feature (metal) size density distribution assumptions and polish rates. Additional challenges included: terminal metal planarization on previously non-CMPed processed parts, accommodation of reference plane (99% density) processing considerations, gap-fill issues previously ignored on terminal layers, compounded edge die impacts, as well as associated non-uniformity and metrology site extrapolation difficulties. Throughput concerns from these ‘large removal processes’ likewise required evaluation within the context of this process development. A multi-head CMP platform with multi-pass (‘semi-situ’ conditioning) process sequence features provided the necessary wafer throughput for process development and qualification. Initial trials where first performed to optimize gap-fill dielectric and bulk SiO2 deposition thicknesses with respect to step height and initial uniformity targets. An initial ‘sacrificial oxide budget’ of 1.6X maximum topography was the chosen starting thickness using CMP process parameters consistent with ILD process layers.
Figure 1.
Typical pre-CMP ‘thick’ terminal metal topography (P22). Nominal 75% gap fill-to-step height deposition + bulk SiO2 shown.
Downloaded from https://www.cambridge.org/core. University of Texas Libraries, on 30 May 2020 at 11:13:04, subject to the Cambridge Core terms of use, available at https://www.cambridge.org/core/terms. https://doi.org/10.1557/PROC-767-F5.7
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EXPERIMENTAL
Nominal ILD CMP process conditions (7.5 psi, 30T, 40C, IC1400, WB20, 12% fumed SiO2 slurry, etc) were compared with ‘high’ throughput (nominal 25% increased downforce, tablespd) conditions on 200mm wafers on a variety of parts. Other contributing variables included: gap-fill + bulk SiO2 ratios/thickness,
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