Cu Plating of Through-Si Vias for 3D-Stacked Integrated Circuits
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1112-E03-06
Cu Plating of Through-Si Vias for 3D-Stacked Integrated Circuits Aleksandar Radisic1, Ole Lühn1, 2, Bart Swinnen1, Hugo Bender1, Chris Drijbooms1, Geert Doumen1, Kristof Kellens1, Wouter Ruythooren1, and Philippe M. Vereecken1 1 IMEC, Kapeldreef 75, 3001 Leuven, Belgium 2 Katholieke Universiteit Leuven, Dept. MTM, Kasteelpark Arenberg 44, 3001 Leuven, Belgium
ABSTRACT In this paper we report on Cu plating of through-Silicon-vias (TSV-s) with a thin Ta film on the field. The thin Ta film is sputtered on top of the Ta barrier/Cu seed, and inhibits Cu plating outside the TSV-s. We show that the use of this Ta-cap and in situ electrochemical monitoring techniques leads to significant savings in plating and polishing time, and thus savings in manufacturing costs of 3D-stacked integrated circuits (3D-SIC).
INTRODUCTION Establishing a cost-effective technology for the metallization of through-Si vias is an important factor in the realization and volume manufacturing of 3D-stacked integrated circuits (3D-SIC). Cu electroplating, which is the preferred technique, should provide not only a voidfree TSV fill, but also short plating time and small overburden. The duration of the plating process is a significant contributor to the overall 3D process cost, and thus needs to be minimized. The overburden, i.e. the thickness of the material deposited on the top surface of the wafer, has to be limited for compatibility with the next processing steps (e.g. chemical mechanical polishing, CMP). The filling results depend on factors such as via dimensions, current density, current waveform, Cu bath composition, properties of the seed, etc. Typical deposition time and overburden for moderately sized 5 µm (diameter) × 25 µm (depth) TSV are between 20 and 60 minutes, and 2.5 and 5.0 µm, respectively. We have explored different approaches to reduce plating time and overburden [1, 2]. In the work presented here, we focus on blocking Cu deposition on the top wafer surface, which coupled with in situ electrochemical methods, results in shorter deposition times and smaller overburden. A thin Ta film on the top surface is used as an inhibitor. Scanning electron microscopy (SEM), focused ion beam (FIB) analysis, and CMP of coupons with Cu filled TSV-s with and without Ta cap, are used to explore the advantages and drawbacks of this approach. EXPERIMENTAL Plating experiments are performed using two-electrode rotating disk electrode (RDE) setup and computer controlled Autolab/Metrohm PGSTAT30 potentiostat.. Working electrode (WE) is the coupon with 5 µm (diameter) × 25 µm (depth) vias. The sample area (i.e. apparent
area of the WE) was either 1.5 cm2 or 16 cm2. The true area of the WE, including area of TSV sidewalls, can be a factor 2 larger than the apparent area, depending on the via density. Cu foil is used as a counter electrode (CE), and is separated from the WE by the diaphragm, which prevents anodic additive breakdown products from affecting deposition process. Volume of the electrolyte in the plating cell is 500 ml. WE is r
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