CW Laser Annealed Small-Geometry NMOS Transistors
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CW LASER ANNEALED SMALL-GEOMETRY NMOS TRANSISTORS A.A. NAEM* , A.R. BOOTHROYD*, AND I.D. CALDER** *Dept. of Electronics, Carleton University, Ottawa, Canada, **Northern Telecom Electronics Ltd., Ottawa, Canada K1Y 4H7
ABSTRACT Small geometry NMOS transistors were fabricated using junctions implanted 2 with 1016 As*/cm @ 180 keV and annealed through 1067 ý of Si0 2 with a ew argon laser. Phosphosilicate glass densification was the only other high temperature step. Channel lengths were varied from 1.3 to 50 jm and channel widths from I to 50,um. Physical characterization of these devices revealed a junction depth of 3000 ý with negligible lateral diffusion. The smallest 2 transistor had approximately a square channel with WxL = lxl.3jim . IDS - VDS characteristics of this device were similar to those of large geometry devices due to counteracting short and narrow channel effects. The threshold voltage was 0.61 + 0.013 V across an entire wafer, while there was no punch-through for VDS < 13 V and no avalanche breakdown for VDS < 14 V. The junctions showed a forward-biased ideality factor of 1.17, 2 and the contact resistance in an 8 x 8 pm area was 1.5S2 to the source/drain regions and 0.591 to laser-recrystallized polysilicon interconnects. It is concluded that cw laser annealing can be used to fabricate small-geometry devices with excellent performance and without any deleterious effects.
INTRODUCTION The fabrication of VLSI MOS devices requires techniques to control dopant redistribution during device processing; both vertically) so that shallow junctions
are
formed,
and
laterally,
to control
the
channel
length.
The
most
promising technique for this purpose is transient annealing, in which redistribution of dopant impurities is reduced because of the short thermal cycle (lOns - lOs). Cw Laser Annealing (LA) is particularly interesting because annealing takes place in the solid phase within times of less than I ms, so that dopant redistribution is essentially eliminated 11]. This feature is attractive for the fabrication of small geometry devices, but there have been few published results on this application. Reported work has been for MOSFET channel lengths (L) of 1.5 to 2.0 pm [2-4], except for one report on devices with L < I pm [5]. In all cases the device width was large; cw LA devices of small area have not previously been reported. In this paper we report on the fabrication, characterization and analysis of small-geometry NMOS transistors. The objectives were to investigate the compatibility of cw LA with IC technology, to relate device performance to the materials and device processing techniques, and to study device size limitations. The devices were fabricated in a standard 5 pm process with three variations: (i) the source and drain (S/D) areas were implanted with arsenic and laser annealed; (ii) densification of the phosphosilicate glass (PSG) was the only high-temperature step after LA; (iii) wafer stepping was used for improved lithography. DEVICE FABRICATION The transistors were fabricated
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