Deep Insight into DC/RF and Linearity Parameters of a Novel Back Gated Ferroelectric TFET on SELBOX Substrate for Ultra
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ORIGINAL PAPER
Deep Insight into DC/RF and Linearity Parameters of a Novel Back Gated Ferroelectric TFET on SELBOX Substrate for Ultra Low Power Applications Ashish Kumar Singh 1 & Manas Ranjan Tripathy 1 & Prince Kumar Singh 1 & Kamalaksha Baral 1 & Sweta Chander 1 & Satyabrata Jit 1 Received: 15 April 2020 / Accepted: 26 August 2020 # Springer Nature B.V. 2020
Abstract In this manuscript, a novel back gated ferroelectric heterojunction TFET on SELBOX substrate (BG-Fe-HJ-STFET) has been proposed. Ferroelectric oxide is considered as gate dielectric material along with SiO2 in a vertical gate stacked manner in the proposed TFET with SELBOX (BG-Fe-HJ-STFET) to improve overall sub-threshold performance of the device. The proposed TFET (BG-Fe-HJ-STFET) is found to achieve a lower sub-threshold swing value of 38.6 mV/decade (below the Boltzmann limit of 60 mV/decade) compared to the SELBOX TFET without ferro dielectric structure (BG- HJ-STFET). Different RF figures of merit such as cut-off frequency, transit time and gain-bandwidth product (GBP) are thoroughly investigated and comparison study is performed for both the TFETs presented for study. Further, the linearity figure of merits (FOMs) like VIP2, VIP3, IIP3, IMD3, and 1-dB compression point has been analyzed for both the TFETs under study. Result shows that the proposed TFET with ferro dielectric gate material (BG-Fe-HJ-STFET) outperforms the SELBOX TFET without ferro dielectric gate material (BG-HJSTFET) in all aforementioned aspects. Performance analysis is carried out using Silvaco TCAD tool for both TFETs structures. Keywords Tunnel field effect transistors (TFETs) . Band-to-band tunneling (BTBT) . Silicon on insulator (SOI) . SELBOX . Linearity . Figures of merit (FOMs)
1 Introduction Commercial aspects of the semiconductor industry have scaled down MOSFET dimension to meet the global demands of increased functionalities in integrated circuits [1, 2]. Although scaling is adopted to meet technology requirements, there are several issues in MOSFETs that need to be addressed as device dimensions have shrunk over the time [3]. Due to the scaling down of MOSFET, a number of adverse effects collectively known as short channel effects (SCEs) like threshold voltage roll-off, drain induced barrier lowering (DIBL), mobility degradation etc. appear in it which can’t be predicted by the
* Satyabrata Jit [email protected] 1
Indian Institute of Technology BHU Varanasi, Varanasi, Uttar Pradesh, India
theory of long channel devices [4]. Researchers are continuously working to look out for novel devices such as HEMT [5], carbon nanotube FET [6], TFET [7–9]. The best alternate device of MOSFETs is tunnel-field effect transistor (TFET) which is needed for the future requirement for low power applications in CMOS technology [7] because of its excellent quality over MOSFETs such as low subthreshold swing (SS), low subthreshold leakage current, and most importantly the absence of short channel effects (SCEs) [7].However, there are two major drawbacks in TFETs such as am
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