Simulation Study and Comparative Analysis of Some TFET Structures with a Novel Partial-Ground-Plane (PGP) Based TFET on
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ORIGINAL PAPER
Simulation Study and Comparative Analysis of Some TFET Structures with a Novel Partial-Ground-Plane (PGP) Based TFET on SELBOX Structure Ashish Kumar Singh 1 & Manas Ranjan Tripathy 1 & Sweta Chander 1 & Kamalaksha Baral 1 & Prince Kumar Singh 1 & S. Jit 1 Received: 11 September 2019 / Accepted: 13 November 2019 # Springer Nature B.V. 2019
Abstract This paper proposes a novel TFET structure namely gate stacked (GS) heterojunction (HJ) partial-ground-plane (PGP) TFET with SELBOX (GSHJ-PGP-STFET) for improving the ON/OFF-state current ratio of the TFET by reducing the OFF-state current while maintaining the ON-state current nearly unaffected. Here we have done a comparative analysis of fully depleted SOI TFET and TFET on SELBOX structure with our proposed device. An extensive TCAD based simulation study has been carried out for investigating the effect of temperature on the subthreshold swing (SS), transfer characteristics, threshold voltage, and ION/IOFF ratio of the given TFET structures. The ION/IOFF ratio and SS are found to be ~1011 and 47 mV/dec respectively which is better over other two structures. Also, the proposed TFET device has improved reliability in terms of smaller effect of temperature on the performance of GSHJ-PGP-STFET as compared to the conventional SELBOX and FD-SOI TFET structures. Keywords Silicon on insulator (SOI) . Selective buried oxide (SELBOX) . Band-to-band tunneling (BTBT) . Tunnel field effect transistor (TFET)
1 Introduction Increased static power dissipation in integrated circuits (ICs) using sub-50 nm channel length MOS transistors are a serious concern due to short channel effects (SCEs) [1–3]. To overcome the situation, TFET is projected as an alternate MOS transistor for low-power VLSI circuits owing to its inherently lower OFF-state current and smaller subthreshold swing (SS), which is below the minimum SS value of the Boltzmann limit of 60 mV/dec obtained in conventional MOSFETs [4, 5]. However, the major drawbacks of TFETs are its low ONstate current and ambipolar conduction [6, 7]. There are several ways, which have been explored for improving the ON current of the TFETs such as gate engineering [8], work function engineering and gate dielectric engineering [9], negative capacitance engineering [10], low band gap engineering [11], * Ashish Kumar Singh [email protected] * S. Jit [email protected] 1
Department of Electronics Engineering, IIT (BHU), Varanasi, Uttar Pradesh 221005, India
source/drain engineering [12], hetero-junction source (drain)/ channel engineering [13] and substrate engineering [14]. Here in this manuscript, we have proposed a new TFET structure obtained by exploring SOI substrate engineering combined with heterojunction (HJ) and gate stacked (GS) high-k/SiO2 oxide structure engineering for improving ION/IOFF ratio of the device. The Ge/Si based source/channel heterojunction [15] and HfO2/SiO2 GS structure is used to enhance the conduction current [16]. The SOI substrate engineering is explored in TFETs for reducing
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