Deep RIE Process for Silicon Carbide Power Electronics and MEMS
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Deep RIE Process for Silicon Carbide Power Electronics and MEMS Glenn Beheim and Carl S. Salupo1 NASA Glenn Research Center Cleveland, OH 44135 1 Akima Corporation Cleveland, OH 44135 ABSTRACT Reactive ion etching (RIE) of silicon carbide (SiC) to depths ranging from 10 µm to more than 100 µm is required for the fabrication of SiC power electronics and SiC MEMS. A deep RIE process using an inductively coupled plasma (ICP) etch system has been developed which provides anisotropic etch profiles and smooth etched surfaces, a high rate (3000 Å/min), and a high selectivity (80:1) to the etch mask. An etch depth of 100 µm is demonstrated. INTRODUCTION Deep RIE processes for SiC are needed to realize the intrinsic advantages of SiC for power electronics and harsh environment MEMS. Etch depths from 10 µm to more than 100 µm are required for trench isolation of SiC power devices, through-wafer vias for advanced packaging schemes, and bulk micromachined SiC structures. The ideal deep RIE process would provide a high rate (at least several thousand Å/min), a highly anisotropic etch profile (e.g. vertical sidewalls with minimal bowing), and smooth etched surfaces. In addition, a high selectivity with respect to an easily deposited and patterned etch mask is required. Deep RIE of SiC has previously been demonstrated using conventional capacitive-type RIE systems [1]. Previously, inductively coupled plasma (ICP) etching has been shown to provide high rates for SiC [2-4]. The effectiveness of ICP for deep etching of SiC is demonstrated here. Key advantages of ICP relative to conventional RIE include: (1) a considerably higher plasma density, which provides a greater flux of energetic ions and reactive species (e.g. atomic fluorine) to the sample; (2) capability for operation at lower pressures, which helps minimize bowing of the etch sidewalls and can also help to eliminate residues caused by the redeposition of nonvolatile etch products (e.g. sputtered mask materials) onto the etched surfaces; (3) capability for independent control of the plasma density and the energy with which ions bombard the sample, through the use of separate RF generators for the coil and substrate bias electrode. EXPERIMENT A: ETCH RATE AND SELECTIVITY MEASUREMENTS For this study deep ICP etching was performed on the silicon face of n-type 6H-SiC using an STS Multiplex ICP [5]. The 10-mm square SiC samples were attached to 100-mm diameter silicon carrier wafers using a drop of photoresist. Typically, the silicon carrier wafer etches at a fairly rapid rate (about 2 µm/min) because Si readily reacts to form a volatile product with atomic fluorine. The sacrificial carrier wafer helps to minimize roughness caused by the sputtering of nonvolatile materials onto the etched SiC surface, which leads to micromasking. The loading effect caused by the silicon carrier wafer varies with different process parameters. For the baseline process (described below), the same etch rate was obtained whether the SiC T8.9.1
Mat. Res. Soc. Symp. Vol. 622 © 2000 Materials Researc
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