Design and Process Issues for Silicon Carbide Power DiMOSFETS
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Design and Process Issues for Silicon Carbide Power DiMOSFETS Sei-Hyung Ryu1, Anant K. Agarwal1, Nelson S. Saks2, Mrinal K. Das1, Lori A. Lipkin1, Ranbir Singh1, and John W. Palmour1 1 Cree, Inc., 4600 Silicon Drive Durham, NC 27703 2 Navel Research Laboratory, 4555 Overlook Avenue Washington, D.C. 20375 ABSTRACT This paper discusses the design and process issues of high voltage power DiMOSFETs (Double implanted MOSFETs) in 4H-silicon carbide (SiC). Since Critical Field (EC) in 4H-SiC is very high (10X higher than that of a Si), special care is needed to protect the gate oxide. 2D device simulation tool was used to determine the optimal JFET gap, which provides adequate gate oxide protection as well as a reasonable JFET resistance. The other issue in 4H-SiC DiMOSFETs is extremely low effective channel mobility (µeff) in the implanted p-well regions. NO anneal of the gate oxide and buried channel structure are used for increasing µeff. NO anneal, which was reported to be very effective in increasing the µeff of SiC MOSFETS in p-type epilayers, did not produce reasonable µeff of SiC MOSFETs in the implanted p-well. Buried channel (BC) structure with 2.7x1012 cm-2 charge in the channel showed high µeff utilizing bulk buried channel, but resulted in a normally-on device. However, it was shown that by controlling the charge in the BC layer, a normally off device with high µeff can be produced. A 3.3 mm x 3.3 mm DiMOSFET with BC structure showed a drain current of 10 A, which is the highest current reported in SiC power MOSFETs to date, at a forward drop of 4.4 V with a gate bias of only 2.5 V. INTRODUCTION High voltage power DiMOSFETs (Double implanted MOSFETs) [1] in silicon carbide (SiC) are very attractive because they have potentials to match silicon IGBTs in the on-state drop, but offer superior switching speed. In SiC power DiMOSFETs, the peak electric field in the blocking region is designed to be approximately 10X higher than that of a Si device with equivalent blocking voltage. This can be detrimental to gate oxide if adequate shielding of electric field is not provided. In this paper, SiC DiMOSFETs with JFET gaps ranging from 2 µm to 5 µm is studied using a 2D device simulator to determine an optimal compromise between gate oxide protection and JFET resistance for 2000V 4H-SiC DiMOSFETs. Another important issue for SiC DiMOSFETs is extremely low surface channel mobility, especially in 4H-SiC. Several methods, such as channel implantations[2] and different anneals for gate dielectric[3,4] have been suggested to improve the MOS channel mobility. These methods were successful for simple devices built in lightly doped p-type epilayers. However, high channel mobility in implanted p-wells, which is more practical for power MOSFETs, have yet to be demonstrated. In this paper, FATFET results in implanted p-wells are obtained for devices with NO anneal and with buried channel structure, and characteristics of power DiMOSFETs fabricated using these techniques are presented. H4.5.1
DEVICE DESIGN AND PROCESSING Figure 1
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