Design of Application-Specific Instructions and Hardware Accelerator for Reed-Solomon Codecs
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Design of Application-Specific Instructions and Hardware Accelerator for Reed-Solomon Codecs Jung H. Lee School of Electrical and Computer Engineering, Ajou University, San 5, Wonchun-Dong, Paldal-Gu, Suwon 442-749, Korea Email: [email protected]
Jaesung Lee Computer System Department, Electronics and Telecommunications Research Institute, 161 Gajeong-Dong, Yuseong-Gu, Taejon 305-350, Korea Email: [email protected]
Myung H. Sunwoo School of Electrical and Computer Engineering, Ajou University, San 5, Wonchun-Dong, Paldal-Gu, Suwon 442-749, Korea Email: [email protected] Received 31 January 2003 and in revised form 6 September 2003 This paper presents new application-specific digital signal processor (ASDSP) instructions and their hardware accelerator to efficiently implement Reed-Solomon (RS) encoding and decoding, which is one of the most widely used forward error control (FEC) algorithms. The proposed ASDSP architecture can implement various programmable primitive polynomials, and thus, hardwired RS codecs can be replaced. The new instructions and their hardware accelerator perform Galois field (GF) operations using the proposed GF multiplier and adder. Therefore, the proposed digital signal processor (DSP) architecture can significantly reduce the number of clock cycles compared with existing DSP chips. The proposed GF multiplier was implemented using the Faraday 0.25 µm standard cell library and it can perform RS decoding at a rate up to 228.1 Mbps at 130 MHz. Keywords and phrases: Reed-Solomon, application-specific DSP, GF multiplier, broadband communication, VLSI architecture.
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INTRODUCTION
With the rapid progress of communication technologies, various broadband access systems have been developed, such as very-high-data-rate digital subscriber line (VDSL) cable modem and wireless LAN, gigabit Ethernet, 4G wireless communication, and so forth. Currently, the software defined radio (SDR) can support various communication standards since a common hardware platform can be adapted for various communication standards by means of software [1]. However, ASIC chips face several limitations such as lack of flexibility for various communication standards, high development costs, and slow time-to-market. Due to these restrictions, implementation methods have been changed to digital signal processor (DSP)-based communication systems that can have advantages in several aspects [2]. Programmable DSPs are greatly improving time-to-market and allowing faster changes and upgrades than hardwired ASIC chips. In addition, DSPs can be used for various applications as well as the Reed-Solomon (RS) decoder. RS codes, providing the capability to efficiently correct
burst errors as well as random error, have been extensively used in various communications and digital data storage systems, such as power line communications (PLC) [3], digital video broadcasting terrestrial (DVB-T) system [4], vestigial sideband (VSB) system [5], cable modem [6], satellite and mobile communications [7], magnetic recording [8], and so forth. This pap
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