Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System
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Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System ¨ 1 Andreas Grubl
· Sebastian Billaudelle1 · Benjamin Cramer1 · Vitali Karasenko1 · Johannes Schemmel1
Received: 17 December 2019 / Revised: 30 April 2020 / Accepted: 20 May 2020 © The Author(s) 2020, corrected publication 2020
Abstract This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS2 65 nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are presented. Accelerated operation of neuromorphic circuits and highly-parallel digital data buses between the full-custom neuromorphic part and the PPU require custom methodologies to close the digital signal timing at the interfaces. Novel extensions to the standard digital physical implementation design flow are highlighted. We present early results from the first full-size BrainScaleS-2 ASIC containing 512 neurons and 130 K synapses, demonstrating the successful application of these methods. An application example illustrates the full functionality of the BrainScaleS-2 hybrid plasticity architecture. Keywords Neuromorphic hardware · Plasticity · Mixed-signal · Verification · Physical design · Monte-Carlo
1 Introduction The design of neuromorphic hardware follows the goal to model parts, or at least functional aspects, of the biological nervous system. A main motivation is to reproduce its computational functionality and especially its ability to efficiently solve cognitive and perceptual tasks. Achieving this requires modeling networks of a sufficient complexity in terms of number of neurons and number of synaptic connections. The brain as a whole and especially its ability to learn and adapt to specific problems is still subject to basic neuroscientific research. Consequently, flexible implementations of learning and plasticity are desirable as well.
Andreas Gr¨ubl
[email protected] Sebastian Billaudelle
[email protected] 1
Kirchhoff-Institute for Physics, Heidelberg University, INF 227, 69120, Heidelberg, Germany
Several neuromorphic hardware systems have been proposed and developed that differentiate themselves in terms of architecture, scaling and learning capabilities, and whether they follow an analog/mixed-signal or purely digital approach. TrueNorth [33] is a neuromorphic chip that integrates 4096 neurosynaptic cores to simulate 1 M neurons and 256 M synaptic connections at biological realtime. It is fully digital and the cores are operated asynchronously. Learning algorithms need to be implemented off-chip; multi-chip topologies have been proposed in [5]. The SpiNNake
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