Design of Dynamic Comparator for Low-Power and High-Speed Applications
Most of the real world signals have analog behavior. In order to convert these analog signals to digital, we need an analog to digital converter (ADC). In the architecture of ADC’s, comparators are the fundamental blocks. The usage of these dynamic compar
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Abstract Most of the real world signals have analog behavior. In order to convert these analog signals to digital, we need an analog to digital converter (ADC). In the architecture of ADC’s, comparators are the fundamental blocks. The usage of these dynamic comparators are maximized because of demand for low-power, area efficient and high-speed ADC’s. The dynamic comparator performance depends on technology that we used. This paper presents the design and analysis of dynamic comparators. Based on the analysis, designer can obtain a new design to trade-off between speed and power. In this paper, a p-MOS latch is present along with a pre-amplifier. p-MOS transistors were used as inputs in pre-amplifier and latch. The circuit operates by specific clock pattern. At reset phase, the circuit undergoes discharge state. During evaluation phase, after achieving enough pre-amplification gain, the latch is activated. The cross coupled connection in the circuit enhances the amplification gain and reduces the delay. This design has optimum delay and reduces the excess power consumption. The circuit simulations are done by using mentor graphics tool having 250 nm CMOS technology. Index Terms: Analog to digital converter (ADC), static comparator, dynamic comparator, two-stage comparator, low-power, high-speed.
Index Terms Analog to digital converter (ADC) Static comparator comparator Two-stage comparator Low-power High-speed
Dynamic
G. Murali Krishna (&) G. Karthick N. Umapathi ECE Department, Jyothishmathi Institute of Technology and Sciences, Karimnagar, India e-mail: [email protected] G. Karthick e-mail: [email protected] N. Umapathi e-mail: [email protected] © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021 A. Kumar and S. Mozar (eds.), ICCCE 2020, Lecture Notes in Electrical Engineering 698, https://doi.org/10.1007/978-981-15-7961-5_110
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1 Introduction Low-power, high-speed ADC’s are the part of different types of applications. Such applications are digital signal processing, digital storage oscilloscopes, cell phones, scientific instruments etc. The comparators are the essential building blocks of various kinds of ADC’s, for example, flash type ADC, pipelined ADC, SAR ADC’s [1–5]. These ADC’s required low-power, high-speed comparators with a less amount of chip area. Since, now-a-days the demand for portable devices is increasing. These devices requires less weight and small size which lead to low-voltage circuits. So, the low-power, high-speed comparators are necessary in ADC’s. The performance of comparators are limited by various factors such as supply voltage, offset voltage, input referred noise, power and delay. The comparator should have less offset voltage for a given supply voltage, less power, optimum delay, kickback noise and high speed for desired performance. In olden days, CMOS amplifiers were implemented as static comparators, however they experiences high power consumption b
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