Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications
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Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications Kimmo Kuusilinna Tampere University of Technology, Korkeakoulunkatu 1, P.O. Box. 553, FIN-33101, Tampere, Finland University of California, Berkeley, Berkeley Wireless Research Center, 2108 Allston Way, Berkeley, CA 94704, USA Email: [email protected]
Chen Chang University of California, Berkeley, Berkeley Wireless Research Center, 2108 Allston Way, Berkeley, CA 94704, USA Email: [email protected]
M. Josephine Ammer University of California, Berkeley, Berkeley Wireless Research Center, 2108 Allston Way, Berkeley, CA 94704, USA Email: [email protected]
Brian C. Richards University of California, Berkeley, Berkeley Wireless Research Center, 2108 Allston Way, Berkeley, CA 94704, USA Email: [email protected]
Robert W. Brodersen University of California, Berkeley, Berkeley Wireless Research Center, 2108 Allston Way, Berkeley, CA 94704, USA Email: [email protected] Received 28 February 2002 and in revised form 10 October 2002 This paper describes the design of a large-scale emulation engine and an application example from the field of low-power wireless devices. The primary goal of the emulator is to support design space exploration of real-time algorithms. The emulator is customized for dataflow dominant architectures, especially focusing on telecommunication-related applications. Due to its novel routing architecture and application-specific nature, the emulator is capable of real-time execution of a class of algorithms in its application space. Moreover, the dataflow structure facilitates the development of a highly abstracted design flow for the emulator. Simulations and practical measurements on commercial development boards are used to verify that real-time emulation of a low-power TDMA receiver is feasible at a clock speed of 25 MHz. Keywords and phrases: rapid prototyping, FPGA, hardware emulation, low power, design flow.
1.
INTRODUCTION
Hardware emulation is one of the most promising approaches to address the problem of constantly growing simulation execution times while simultaneously retaining high confidence on the results. Accurate simulations of large systems can be extremely slow and the reduced reliability of faster, more abstract simulation models cannot always be tolerated [1]. Especially logic-level development and verification of systems-on-a-chip (SoC) designs require advanced methods. The purpose of the Berkeley Emulation Engine
(BEE) project is to be able to emulate in real-time the digital portion of low-power communication chips and systems, while providing a robust and flexible interface to analog radio front-ends. Figure 1 depicts the BEE infrastructure. The actual emulation is done with the BEE processing units (BPUs). Multiple BPUs can be connected together to form a larger emulation platform; a four-BPU BEE is shown in Figure 1. Each of the BPUs has a separate connection to the host server through the dedicated Ethernet. The main purpose of the server is
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