Designing Ultra-Low-k Dielectric Materials for Ease of Patterning
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Designing Ultra-Low-k Dielectric Materials for Ease of Patterning G. A. Antonelli1, G. Jiang2, M. Sriram2, K. Chattopadhyay3, W. Guo4, H. H. Sawin4 1. External Research and Development, Albany, NY 12203 USA 2. PECVD Business Unit, Novellus Systems, Tualatin, OR, 97062 USA. 3. Customer Integration Center, Novellus Systems, San Jose, CA, 95134 USA. 4. Department of Chemical Engineering, Massachusetts Institute of Technology, Cambridge, MA, USA. ABSTRACT Organosilicate materials with dielectric constants (k) ranging from 3.0 to 2.2 are in production or under development for use as interlayer dielectric materials in advanced interconnect logic technology. The dielectric constant of these materials is lowered through the addition of porosity which lowers the film density, making the patterning of these materials difficult. The etching kinetics and surface roughening of a series of low-k dielectric materials with varying porosity and composition were investigated as a function of ion beam angle in a 7% C4F8/Ar chemistry in an inductively-coupled plasma reactor. A similar set of low-k samples were patterned in a single damascene scheme. With a basic understanding of the etching process, we will show that it is possible to proactively design a low-k material that is optimized for a given patterning. A case study will be used to illustrate this point. INTRODUCTION Plasma processing is used widely in advanced interconnect integration, including deposition of thin films, the etching of trenches and vias in those films, photoresist strip, and post-etch cleaning. During plasma-based etch processes, reactive neutral species and energetic ions impinging on the feature surface and sidewall impart morphological changes to all layers of a process stack, including the photoresist, hard mask, inter-layer dielectric (ILD), and the substrate forming anisotropic striations on the feature sidewall. This line-edge roughness (LER) has become more of a concern as the critical dimensions shrink to the sub-100 nm scale [1-4]. Maintaining smooth sidewalls prior to substrate etch is desirable as it leads to smoother sidewalls after ILD etch. Low-dielectric-constant (low-k) materials deposited by plasma enhanced chemical vapor deposition (PECVD) have been broadly used to replace silicon dioxide as the ILD in the integration of ultra-large-scale integrated circuitry in order to reduce and thus improve the RC time delay. Organosilicate glasses (OSG) are one of the most common classes of low-k materials. OSG has a silicon dioxide matrix interrupted by the presence of organic functional groups such as methyl (-CH3) groups [5]. These moieties open up the matrix of the material creating well-defined pores. The porosity lowers the density and the dielectric constant relative to a conventional PECVD SiO2. However, this porosity has adverse effects such as weakening the mechanical stability of the matrix, introducing a greater degree of roughness on the surface, allowing a fast diffusion path, and initiating undesirable patterning during proce
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