Diffusion Barriers for Mobile Ions in 256M DRAMs
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ABSTRACT In this study, we investigate the diffusion of mobile ions through thin PSG or SiN layers using secondary ion mass spectrometry (SIMS). The diffusivity of Na through either layer is about 100,OOOX slower than through Si0 2. Hence, thin layers of these materials are effective barriers for short anneals at 400'C. However, there is significant diffusion of both Na and K through these layers at 550'C. This suggests that improved cleans will be required to remove mobile ion contamination after interconnect processes.
INTRODUCTION Alkali ions such as Na and K drift in electric fields at relatively low temperatures in Si0 2, and hence can cause undesirable threshold voltage shifts in field effect transistors [1,2]. As a result, there have been many publications on mobile ion contamination in integrated circuits [212]. Two of the most common sources of mobile ion contamination are photoresist [3-5] and the slurries used for chemical mechanical polishing of Si0 2 [6]. Mobile ions from these processes can be minimized by using wet cleans based on HCI:H 20 2 , H2SO 4 :H20 2, or dilute HF chemistries [4-7]. However, these cleans generally cannot be used during processing of interconnects, making it difficult to completely remove the contaminants. Because of this, diffusion barriers such as SiN and/or gettering layers such as P-doped glass (PSG) or B and Pdoped glass (BPSG) are commonly used to prevent mobile ions from diffusing into the gate regions [8-12]. However, low temperature (undoped) dielectrics such as high density plasma (HDP) Si0 2 are being investigated as replacements for BPSG [19]. In addition, for advanced dynamic random access memories (DRAMs), the minimum dimensions are approaching 0.15 gim, requiring thinning of all the layers including the mobile ion barriers. Hence, it is important to determine the effectiveness of these thin barriers. In this study, we investigate the diffusion of mobile ions through thin PSG or SiN layers.
EXPERIMENT Two types of samples were fabricated; "single layer" Si0 2 samples (50 nm Si0 2 / contamination / 700 nm Si0 2 / Si substrate) for contamination studies and multilayer dielectric samples for diffusion barrier studies. In all cases, the dielectrics were deposited by plasma enhanced chemical vapor deposition (PECVD) at 400 'C on 200 mm Si wafers, to simulate interlevel dielectric processes. For the multilayer samples a buried contamination layer was formed near the bottom of a dielectric stack and a PSG gettering layer was formed near the top of the stack, with different diffusion barriers (no barrier, 50 nm PSG, or 25 nm SiN) in between the contamination layer and the gettering layer (Figure 4). The PSG gettering layer provides a driving force for mobile ion diffusion towards the top of the film. The PSG gettering layer was 229
Mat. Res. Soc. Symp. Proc. Vol. 564 ©1999 Materials Research Society
placed at the top of the stack rather than at the bottom as a precaution, in the event there were problems with drift of the mobile ions during SIMS analysis (see below).
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