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able, because it leads to increase in parasitic source and drain resistance and prevents performance improvement of MOSFETs by scaling. Source and drain junctions for sub 0.1 Pm CMOS devices are fabricated with As implantation whose energy is less than 10 keV [1, 2]. However, fundamental characteristics of As implanted layers, such as junction depth and sheet resistance, have not been evaluated sufficiently in these cases. As an alternative to As implantation, we have investigated Sb implantation and have achieved reduction in junction depth without increase in sheet resistance [3]. In the same report, we described that Sb piles up at the SiO 2/Si interface and the pileup results in dopant loss. When the implantation energy was reduced down to 5 keV, much increase in the sheet resistance was observed for both Sb and As probably due to the pileup. In this report we add some quantitative data concerning the dopant loss and its time dependence to clarify the influence of the pileup and other dopant loss mechanisms. EXPERIMENT Antimony or As were implanted into Si wafers through 5 nm thick screen oxide. Implantation energies were mainly 5 or 10 keV. Implantation dose was mainly 1x10 14 cm- 2 . After removal of the screen oxide the wafers were annealed at 850 'C for 30 min in N2 ambient. During introduc23 Mat. Res. Soc. Symp. Proc. Vol. 532 ©1998 Materials Research Society

tion of the wafers into an annealing furnace the Si surface is oxidized for 2 nm because of 02 pulling in from the air. Depth profiles of Sb or As were obtained by SIMS analysis. RESULTS Potential for Ultra Shallow Junction Formation Figures 1 (a) and I (b) show As and Sb depth profiles, respectively. The implantation energy and the dose were 10 keV and lx1014 cm-2 , respectively. SIMS profiles were obtained at 3 process steps, as implanted, after anneal and after HF dip as illustrated in Fig. 2. Junction depth after annealing, defined at a substrate doping concentration of lx 1018 cm-3 using depth profiles, are 36 nm and 18 nm for As and Sb, respectively. Concerning the as implanted cases, depths obtained with the same definition are 27 nm and 16 nm for As and Sb, respectively. It is clear that the superiority of Sb against As in the junction depth is a result of smallness of diffusivity. Dopant Loss Evaluation After annealing, pileup is clearly observed for both As and Sb. By dipping wafers in HF acid and removing the 2 nm thick oxide, most of the pileup disappears, indicating the dopant loss. This result indicates that piled up As or Sb are located inside the Si0 2 or at the Si0 2/Si interface. SaiHalasz et al. [4] have reported that Sb implanted into the middle of SiO 2 formed on Si piles up at the Si0 2 surface and the Si0 2/Si interface [4]. So we believe that pileup occurs in the vicinity of the interface. The distribution tail of pileup seen in the SIMS depth profiles is due to the SIMS analysis depth resolution limit. In our experiment, the Si surface is slightly oxidized during annealing. However, since the pileup occurs under nonoxidizing