Dynamic workload-aware DVFS for multicore systems using machine learning
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Dynamic workload-aware DVFS for multicore systems using machine learning Manjari Gupta1 · Lava Bhargava1 · S. Indu2 Received: 28 January 2020 / Accepted: 24 September 2020 © Springer-Verlag GmbH Austria, part of Springer Nature 2020
Abstract With growing heterogeneity and complexity in applications, demand to design an energy-efficient and fast computing system in multi-core architecture has heightened. This paper presents a regression-based dynamic voltage frequency scaling model which studies and utilizes workload characteristics to obtain optimal voltage– frequency (v–f) settings. The proposed framework leverages the workload profile information together with power constraints to compute the best-suited voltage– frequency (v–f) settings to (a) maintain global power budget at chip-level, (b) maximize performance while enforcing power constraints at the per-core level. The presented algorithm works in conjunction with the workload characterizer and senses change in application requirements and apply the knowledge to select the next setting for the core. Our results when compared with two state-of-the-art algorithms MaxBIPS and TPEq achieve the average power reduction of 33% and 25% respectively across 32-core architecture for PARSEC benchmarks. Keywords Dynamic voltage frequency scaling · Workload decomposition · Multicore processors · Energy-performance tradeoff · Machine learning Mathematics Subject Classification 62J05 · 68M20
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S. Indu [email protected] Manjari Gupta [email protected] Lava Bhargava [email protected]
1
Malaviya National Institute of Technology, Jaipur, India
2
Delhi Technological University, Delhi, India
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M. Gupta et al.
1 Introduction There has been an upsurge in the demand for battery-operated devices due to their widespread applications and increased usability across various sectors. Minimizing power consumption and maximizing performance is rapidly becoming a fundamental customer requirement. This has an added advantage of the improvement in chip’s reliability and hence longer lifetime which has been an additional concern. Dynamic voltage frequency scaling (DVFS) has been universally adopted as a low-power technique while fulfilling the performance requirements. Modern-day processors like Intel XScale, Transmeta Crusoe, and AMD Athlon are equipped with in-built DVFS capability [1]. The main objective of DVFS is to supply “just enough” circuit speed for processing system workload whilst attaining the desired throughput and minimizing energy consumption simultaneously [2]. Since the power consumption of a processor is cubically reliant on the operational frequency (E α Capacitance × voltage2 × frequency × cycles), management of clock frequency directly results in energy-savings. Figure 1 illustrates the effect of DVFS on power consumption and execution time of a workload [3]. With no DVFS applied, let t1 be the time a task takes to complete at the highest frequency ( f 1 ). Let Psys f 1 represent the power consumed by this task. Pidle f 1 signify the CPU/core power consumptio
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