Effects of Silicon Implantation and Processing Temperature on Performance of Polycrystalline Silicon Thin-Film Transisto
- PDF / 969,842 Bytes
- 6 Pages / 420.48 x 639 pts Page_size
- 82 Downloads / 206 Views
EFFECTS OF SILICON IMPLANTATION AND PROCESSING TEMPERATURE ON PERFORMANCE OF POLYCRYSTALLINE SILICON THIN-FILM TRANSISTORS FABRICATED FROM LOW PRESSURE CHEMICAL VAPOR DEPOSITED AMORPHOUS SILICON Anne Chiang, Tiao Y. Huang, I-Wei Wu, and Mark H.Zarzycki Xerox Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304 Mario Fuse Fuji Xerox Co., Ltd., 2274 Hongo Ebina-Shi Kanagawa-Ken, 243-04 Japan
ABSTRACT Silicon implantation has been found to dramatically enhance the grain size of polysilicon crystallized from LPCVD a-Si by retarding the nucleation process at the substrate interface. Corresponding improvement in TFT device performance was also observed, resulting in field effect mobilities as high as 109 cm2/Vs in devices with 1000 A thick Si active layer. This effect is more significant in device fabrication processes with higher temperature, possibly due to increasingly efficient removal of implant related defects. INTRODUCTION Polysilicon thin-film transistor (TFT) technology has been actively investigated recently for its application to large-area electronics. The high mobilities achievable in polysilicon make it an attractive alternative to the a-Si TFTs traditionally used in LCD panels [1,2] and document input scanners [3]. Even more interesting is the pixel-wise logic and signal processing functions potentially realizable with polysilicon TFTs integrated on the large area substrate. The effective speed in highly parallel operations would be at least comparable to those with off-board bulk Si ICchips in serial operation. in order to achieve the high speed in polysilicon TFTs required for such complex circuit functions,
several processing techniques have been developed to enhance device performance. These include passivation of grain boundaries by hydrogenation [4], recrystallization from Si implant amorphized polysilicon to obtain larger grains [5.6], and reduction of the active Si layer thickness to minimize areal trap density [7.8]. The highest mobility of 100 cm2/Vs was achieved with a combination of all three techniques in a 200
A thick polysilicon TFT
[7].
We will report on a grain size enhancement effect in Si-implanted and crystallized LPCVD amorphous-Si which has resulted in field effect mobilities up to 109 cm2/Vs in 1000 A thick.Si films. The grain size enhancement mechanism will be explored and the corresponding device performance improvement will be discussed in terms of processing temperature and hydrogenation. Si IMPLANTION AND CRYSTALLIZATION OF LPCVD a-Si It is well known that LPCVD Si films deposited at tempereatures below 590 *Care amorphous, while those deposited above 600 'C are polycrystalline [9]. TFTs fabricated with the former film after crystallization are much higher in performance than those fabricated from the latter due to the larger grain size and smoother Si/Si0 2 interface of the initially amorphous films [10,11]. LPCVD a-Si is thus the preferred starting material for TFT. The LPCVD a-Si film transforms readily into polysilicon with a strong {111} texture by the
Data Loading...
