Effects of the Ultra Low Diluted Ceria-Based Slurry on the Planarization Characteristics of Multi-Layer Exposed Surfaces
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0921-T05-20
Effects of the Ultra Low Diluted Ceria-Based Slurry on the Planarization Characteristics of Multi-Layer Exposed Surfaces Kyung Ho Hwang, Jae Gon Choi, Myung Shin Lee, Yong Soo Choi, Geun Min Choi, and Yong Wook Song R & D Division, Hynix Semiconductor Inc., Ami-ri Bubal-eub, Icheon-si, Kyoungki-do, 467-701, Korea, Republic of ABSTRACT Planarization characteristics of ultra low diluted Ceria (CeO2) based slurry, especially a multi-layered Chemical Mechanical Polishing (CMP) process, have been studied. The multilayer represents the polished film consists of more than two different materials, so that, more than two different materials are exposed to the polished surface. In this work, ultra low diluted ceria based slurry was introduced to minimize micro-dishing effect of the process such as a storage node contact and a bit line contact in 80nm feature sized DRAM device, which has multi-layer film surfaces. As a result, we can minimize micro dishing of silicon dioxide and polycrystalline silicon at memory cell area, and silicon dioxide dishing at peripheral area. INTRODUCTION As the minimum feature size of microelectronic devices reaches below 80 nm and beyond technology node, the multi-layered CMP process is strongly required for isolating adjacent contact. In this case, the CMP process requirements, such as perfect planarization, perfect cellto-cell isolation, and defect-free surface become more stringent. In the multi-layered CMP process with the removal rate difference of each exposed film, however, it is difficult to avoid micro dishing phenomena and to minimize various kinds of defects generated from the polishing process. In the DRAM manufacturing process, the target of CMP process roughly can be divided into two groups, such as planarization only, and planarization with isolation between contact-tocontact. A storage-node contacts (SNC) and a bit-line contact (BLC) isolation CMP are typical processes for planarization with isolation. Figure 1 shows a schematic cross-sectional and top view of this contact isolation CMP process. In this case, polycrystalline silicon (denoted as polySi), silicon nitride (Si3N4) and silicon dioxide (SiO2) film are exposed after the CMP process. When conventional oxide slurry is employed to this CMP process, the surface has the issue of SiO2 and poly-Si dishing, because conventional oxide slurry has higher CMP removal rate of SiO2 and poly-Si than that of Si3N4. High pH value of conventional oxide slurry causes dissolution of both films compared to Si3N4 film. Figure 2 shows CMP induced dishing at memory cell area and peripheral area of DRAM device. CMP induced micro dishing causes various kinds of integration issues such as polishing residues and some problems in the following photolithography patterning process. After all, these issues can lead to critical fail in the device operation sequence and low production yield. In this work, ultra low diluted ceria based slurry was introduced to minimize micro dishing after poly-Si, Si3N4 and SiO2 films exposed multi-layered CMP
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