Efficient implementation of quantum arithmetic operation circuits
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nuary 2021 Vol. 64 No. 1: 210332 https://doi.org/10.1007/s11433-020-1616-2
Efficient implementation of quantum arithmetic operation circuits 1,2,3*
Heng Fan 1
2
Institute of Physics, Chinese Academy of Sciences, Beijing 100190, China; CAS Center for Excellence in Topological Quantum Computation, University of Chinese Academy of Sciences, Beijing 100190, China; 3 Songshan Lake Material Laboratory, Dongguan 523000, China Received August 14, 2020; accepted September 8, 2020; published online November 26, 2020
Citation:
H. Fan, Efficient implementation of quantum arithmetic operation circuits, Sci. China-Phys. Mech. Astron. 64, 210332 (2021), https://doi.org/10.1007/ s11433-020-1616-2
Realization of robust quantum computing is a tremendous task. On one hand, one must reduce errors as many as possible using various means [1-3]; on the other hand, one may make large error rates tolerable via fault-tolerant implementation. In achieving tolerant against noises, the cost to pay is the increased number of gates used. Therefore, an efficient implementation of fault-tolerant gates is crucial. As already evidenced, Clifford gates with a T gate can form a universal set of fault-tolerant gates. The optimal implementations for Toffoli and Fredkin gates were first proposed in ref. [4]. In a recent study, Li et al. [5] constructed efficient gates TR1, TR2, PG1, PG2 and PG3 using Clifford and T circuits. The TR1 and TR2 gates realize the following tasks: TR1 : C B A
A. B
C A
TR2 : C B A
A. B
C B A
Table 1
B A, B,
where the symbols “.” and “ ” represent multiplication and exclusive-or operators, respectively, and B is equal to (1 B). Both TR1 and TR2 enable the implementation of the sum and carry of binary subtraction. While the Peres gate and its variants, denoted as PG1, PG2, and PG3, enable the implementation of the sum and carry of binary addition as follows: PG1 : C B A
A. B
C A
B A,
PG2 : C B A
A. B
C B A
PG3 : B C A
B A. B
C A
B, B.
These gates are constructed for the efficient implementation of arithmetic operations with low total depths and total counts compared with previous best-known work. Here Cost refers to the number of basic gates required to realize the gates. Comparison of performance indicators in Table 1
Performance indicators of the Peres, TR, their variants, Toffoli, and Fredkin gates
Indicators
Toffoli
Fredkin
TR1
TR2
PG1
PG2
PG3
Cost
5
7
4
4
4
4
4
Delay
5
7
4
4
4
4
4
T-depth
3
3
3
3
3
3
3
Total depth
9
11
9
9
9
9
9
T-count
7
7
7
7
7
7
7
Total count
16
18
15
15
15
15
15
*
Corresponding author (email: [email protected])
© Science China Press and Springer-Verlag GmbH Germany, part of Springer Nature 2020
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H. Fan
Sci. China-Phys. Mech. Astron.
shows that these five gates have the smaller cost, delay, Tdepth, total depth, T-count and the total count. As a short summary, Li et al. [5], proposed an implementation of a series of gates by using Clifford and T circuits, which are fault-tolerant. The i
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