Efficient Realization of Sigma-Delta ( - ) Kalman Lowpass Filter in Hardware Using FPGA
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Efficient Realization of Sigma-Delta (Σ-Δ) Kalman Lowpass Filter in Hardware Using FPGA Saman S. Abeysekera and Charayaphan Charoensak School of Electrical & Electronic Engineering, Nanyang Technological University, Block S1, Nanyang Avenue, Singapore 639798 Received 8 December 2004; Revised 3 August 2005; Accepted 12 September 2005 Recommended for Publication by Peter Handel Sigma-delta (Σ-Δ) modulation techniques have moved into mainstream applications in signal processing and have found many practical uses in areas such as high-resolution A/D, D/A conversions, voice communication, and software radio. Σ-Δ modulators produce a single, or few bits output resulting in hardware saving and thus making them suitable for implementation in very large scale integration (VLSI) circuits. To reduce quantization noise produced, higher-order modulators such as multiloop and multistage architectures are commonly used. The quantization noise behavior of higher-order Σ-Δ modulators is well understood. Based on these quantization noise characteristics, various demodulator architectures, such as sinc filter, optimal FIR filter, and Laguerre filter are reported in literature. In this paper, theory and design of an efficient Kalman recursive demodulator filter is shown. Hardware implementation of Kalman lowpass filter, using field programmable gate array (FPGA), is explained. The FPGA synthesis results from Kalman filter design are compared with previous designs for sinc filter, optimum FIR filter, and Laguerre filter. Copyright © 2006 Hindawi Publishing Corporation. All rights reserved.
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INTRODUCTION
Recently, Σ-Δ modulation techniques have been successfully applied in numerous applications such as low-cost and highresolution A/D and D/A converters, software-defined radio [1, 2], correlators, multipliers, and synchronizers [3]. One main reason for popularity of Σ-Δ modulation lies in its ability to trade bandwidth with quantization noise. ΣΔ circuit allows reduction in hardware complexity, while at the same time provides higher signal resolution. The fewer number of bits removes the need for expensive multibit circuitry such as multipliers and hence decreases the overall circuit complexity. In some cases, multipliers can be entirely eliminated from the circuit [4]. These features make Σ-Δ based circuits attractive for complete system-on-chip designs [3, 5, 6]. The applications of Σ-Δ require proper lowpass filters as demodulators to remove quantization noise. Various demodulator filter architectures, such as optimum FIR filter, sinc filter, and Laguerre filters are well understood and reported in literature [7–10]. In this paper, theory and efficient realization of a Kalman lowpass filter is described and implemented in hardware using field programmable gate array (FPGA). The simulation and synthesis results of FPGA implementation of the filter
are reported. Comparison of synthesis results among various FPGA filter designs including sinc filter, optimum FIR filter, Laguerre filter, and Kalman filters, both down-sampled and full-rate
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