Efficient Architecture for the Realization of 2-D Adaptive FIR Filter Using Distributed Arithmetic
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Efficient Architecture for the Realization of 2-D Adaptive FIR Filter Using Distributed Arithmetic Prabhat Chandra Shrivastava1 Amit Dhawan1
· Prashant Kumar1 · Manish Tiwari1 ·
Received: 3 October 2019 / Revised: 17 August 2020 / Accepted: 4 September 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract This paper presents an efficient architecture for two-dimensional (2-D) adaptive FIR filter architecture using the distributed arithmetic (DA) algorithm. DA-based filter architectures essentially require look-up tables (LUT). In the proposed filter architecture, RAM- or ROM-based LUT is replaced by adders- and logic gates-based structure that generates the LUT value corresponding to the input. Therefore, the MAC unit requires fewer logic gates and adders in DA-based realization. In addition, the memory sharing concept in architecture reduces the delay elements. Moreover, the complexity of the LUT hardware of higher-order filters is reduced by parallelly dividing the internal MAC block for the DA decomposition which offers a higher degree of modularity and parallelism in the proposed architecture. Further, 2-D delayed LMS algorithm is used for the updation of the filter coefficient weights. Furthermore, twostage pipelining is used to reduce the critical path of the architecture and it also makes critical path delay independent of the order of the filter. ASIC synthesis results reveal the advantages of the proposed structure by reducing the area, power, ADP and EDP by 54%, 48.19%, 55% and 49%, respectively, as compared with the existing architecture for filter size 8 × 8. Keywords 2-D adaptive filter · Distributed arithmetic · Hardware-based LUT · Multiplier-less filters · Raster scanning · 2-D delayed LMS algorithm
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Prabhat Chandra Shrivastava [email protected] Prashant Kumar [email protected] Manish Tiwari [email protected] Amit Dhawan [email protected]
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Department of Electronics and Communication Engineering, MNNIT-Allahabad, Prayagraj, UP 211004, India
Circuits, Systems, and Signal Processing
1 Introduction In recent years, the two-dimensional (2-D) digital systems have attracted increasing attention due to their theoretical as well as application importance in digital filtering. The main feature of a 2-D filter is that the system dynamics is a function of two independent variables as a result of information propagation in two independent directions [31]. The 2-D adaptive digital filters have a wide range of communication and DSP applications such as adaptive equalizer, image enhancement, image compression and so on [7, 14, 27]. The 2-D adaptive digital filters can conveniently be simulated on general-purpose computers but the process may not be suitable for real-time applications. Hence, applications such as real-time image processing that involve a high data rate needs dedicated hardware structures to meet the high throughput demand. Hardware structures for the adaptive filter require weight updation algorithm to compute the filter coefficient in each iterati
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