Electrical Characterization of Highly Strained Ultrathin InAs/GaAs Quantum Wells
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151 Mat. Res. Soc. Symp. Proc. Vol. 326. ©1994 Materials Research Society
Experimental Figure 1 shows the schematics of the structures used in this study. The first (sample A) consisted of 2800A n-GaAs (2x10' 6 cm- 3 ) followed by 30 A undoped GaAs, 1 ML InAs, 30 A undoped GaAs and finally a 2800A n-GaAs (2x10 16 cm- 3 ) layer. Sample B was identical to the first but was grown without the InAs monolayer. In both samples a 0.5 gim undoped GaAs buffer layer was grown. Epitaxial growth was carried out in a Vacuum Generator V80H MBE system using elemental sources. Semi-insulating GaAs (100) quarter 3" substrates were prepared by first degreasing and etched using a standard solution of H2 SO 4 , H2 0 2 and H20, mounted onto 3" Si substrates using indium solder and loaded in In-free holders for growth. The substrate temperature used during the growth of GaAs was 580'C as measured by an optical pyrometer. A GaAs growth rate of 0.8 jtm/hr and InAs growth rate of 0.5 monolayers/sec were used as determined by reflection high-energy electron diffraction (RHEED) intensity oscillations. For the growth of the InAs monolayer the substrate was ramped to 420'C in an As4 flux after the growth of the 30A undoped GaAs. The InAs was deposited in 2 layers of 0.6 monolayers with a 2 minute annealing step after each layer. Prior to ramping the substrate to 580'C for the growth of the top GaAs layers, 3 monolayers of GaAs were deposited on top of the InAs layer at 420'C to prevent desorption of In during ramping. This method is similar to that used by Ploog et al. 8 to incorporate fractions of a monolayer of InAs in a GaAs matrix and to control the InAs/GaAs and GaAs/InAs interfacial quality. 2800A n-GaAs
2800A n-GaAs 30A i-GaAs 1ML InAs 30A i-GaAs
60A i-GaAs
2800A n-GaAs
2800A n-GaAs
5000A i-GaAs
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SI GaAs sub. Fig.1
5000A i-GaAs SI GaAs sub.
Sample A Sample B Schematics of the InAs monolayer structure grown by MBE. Sample A consists of one monolayer InAs, while Sample B does not.
The electrical test devices were fabricated by standard photolithography and lift-off processes with the electron beam evaporated Al circular Schottky contact (600 gim in diameter) on the top epitaxial GaAs confining layer. The ohmic contact was prepared in a similar manner using Ni/GeAu metalization and in the shape of a guard ring surrounding the Schottky barrier. The current-voltage (I-V) characteristics of the diode shows a leakage current in the low nanoampere or even mid-picoampere range for the given applied reverse bias in later C-V and DLTS measurements. For the I-V and C-V measurements, an Hewlett Packard 4145B semiconductor parameter analyzer (SPA) and an HP4275 Multi-Frequency LCR meter controlled by an HP9836 computer were used. A lock-in amplifier DLTS set-up is used to measure the localized energy state within the InAs quantum well. The Schottky diodes were mounted on a sample holder in a closed-cycle cryostat with a temperature variation capability from -11 to 400 K. The transient capacitance signal is recorded by a Booton 72B capacit
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