Electromigration induced microstructure and morphological changes in eutectic SnPb solder joints
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Simultaneous direct current stressing with thermal aging accelerates the migration of conducting species resulting in significant microstructural coarsening. Because of the synergistic fields influence, such coarsening begins from the anode and propagates toward the cathode. Prolonged current stressing with 104 A/cm2 at 150 °C causes the inter-lamellar eutectic SnPb to become a two-layer structure, with a Pb-rich layer adjacent to the anode and an Sn-rich layer adjacent to the cathode. This mass movement causes hillock/valley formation, and the extents of such surface undulations increase with increases in the time duration of current stressing as well as with the joint thickness. In thinner solder joints these events occur sooner, although the extents of surface undulations depend on the thickness of joints. In addition, Cu present in the substrate and in the intermetallic layer at the cathode migrates to form Cu6Sn5 within the Sn-rich layer, in a region close to the Pb-rich layer.
I. INTRODUCTION
Electromigration, which is associated with atomic migration resulting from electron wind, is a serious concern in electronics encountering high current densities. Such migration quite often results in manifestations of visible surface features. Studies carried out using thin strip configuration have shown that eutectic SnPb exhibited a critical current density for electromigration that is two orders of magnitude less than that for the single phase Al or Cu at comparable homologous temperatures.1 According to recent results reported in literature,2 the critical current density that can initiate a visible atom drift in a 370 m long eutectic SnPb strip is 8.5 × 103 A/cm2 at 100 °C. Using the current 0.2 A per bump design rule,1 the average current density in one single flip-chip joint with the diameter of 100 m is about 2.5 × 103 A/cm2. Although this is lower than the reported threshold value, the extreme thin-thick divergence (∼10−2) in the interconnect-to-bump geometry can induce “current crowding” in solder around the cathode region.3 The current density in this region has been estimated to be one order of magnitude higher than the average imposed value.3 Hence, failures in flip-chip joints involving such localized high current density have been widely reported in recent years.1,3–9
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Address all correspondence to this author. e-mail: [email protected] DOI: 10.1557/JMR.2007.0413 J. Mater. Res., Vol. 22, No. 11, Nov 2007
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To circumvent this risk, modifications to joint geometry to reduce high current density gradients within the solder have been developed.10,11 There are still several potential reliability issues that can arise in these designs with imposition of higher current densities, because of the continuous miniaturization of electronics. Because most of the electronic solders used in interconnects are multiphase materials to accommodate several manufacturing and service related issues, migration of several conducting species, and microstructural evoluti
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