Elimination of slip lines in capless rapid thermal annealing of GaAs
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I. INTRODUCTION Rapid thermal annealing (RTA) is known to be a promising technique for ion implantation dopant activation in GaAs, where As outdiffusion is a major concern. Not only are the electrical properties and uniformity of the GaAs wafers annealed with RTA as good as or better than wafers using a furnace anneal (FA), but also the throughput of RTA is better than that of FA, where an As overpressure is needed.1 It has also been shown that performance of devices made using RTA is better than those fabricated using a FA. Power FET wafers annealed in an RTA gave sharper profiles, higher / s a t , greater peak electron concentrations, and better mobilities than those annealed in a furnace.2 Furthermore, RTA has the advantage over FA for self-aligned gate modulation-doped A L . G a ^ x As/GaAs heterostructures. The limited dopant diffusion during RTA compared to the dopant diffusion in FA allows such complex structures to be fabricated with little degradation of device performance.3 Recently, GaAs MESFET's were successfully fabricated where a buried ;? layer was formed beneath the Si channel by coimplantation of Si and Be. RTA was used for electrical activation in this scheme and good device data resulted. These results can be partially attributed to the ability to activate the two species at the same time with little diffusion during RTA. 4 Although RTA shows much promise, as described above, there is a recurring problem of slip line production in whole 2 in. wafers annealed using RTA. 1 5 6 The presence of these slip lines causes problems in later processing steps, particularly photolithography. Crystallographic slip is caused by compressive thermal stresses induced by temperature gradients from the center to the edge of the wafer during the cooling period of the RTA process. The edge of the wafer, having three surfaces free to radiate heat, cools more rapidly than the center of J. Mater. Res. 3 (5), Sep/Oct 1988
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the wafer that can only cool from the top and bottom. A second source creating temperature gradients during RTA cooling is warpage or ripples in the structure supporting the wafer being annealed. These support structures have traditionally been Si wafers that also incur slip and warpage during the cooling of the RTA. Although the Si support may retain good thermal contact with the wafer being annealed for a few runs, after a very short time this Si wafer warps and is no longer useful. The problem of crystallographic slip has been addressed by several authors, and a few different techniques have been proposed. These techniques include the use of a single 3 in. laser-drilled Si guard ring around a GaAs wafer with a Si3N4 cap,6 a set of two annular Si rings around a capless GaAs wafer,7 and a set of 4 in. sheets of graphite where one is used as a base, one as a guard ring, and one as a cap surrounding the GaAs wafer.8
II. EXPERIMENTAL CONSIDERATION To obtain reproducible and reliable slip-free RTA of GaAs wafers, it is first critical to use a strong support structure that d
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