Ellipsometry Measurement Accuracy of Gate Oxides under Polysilicon
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Ellipsometry Measurement Accuracy of Gate Oxides under Polysilicon Gary Jiang, Don Pelcher, Daewon Kwon, Jana Clerico, and George Collins Rudolph Technologies, Inc. One Rudolph Rd, Flanders, NJ 07836 ABSTRACT Precisely controlling the thickness of ultrathin silicon dioxide (SiO2) gate dielectric films is critical for high yield advanced generation semiconductor manufacturing. Advanced methods for producing ultrathin gates deposit both the gate dielectric and the polysilicon (poly-Si) gate electrode in a single cluster tool. This avoids the opportunity for adsorption of molecular airborne contamination (MAC) between deposition of the two layers, but necessitates measuring gate oxide thickness through a thick poly-Si layer. Variations in poly-Si grain size, amorphous silicon content, and roughness, make it very difficult to model the optical feedback in the visible spectral range to resolve ultrathin (10-20 Å) gate oxides with sufficient accuracy and repeatability for process control. This paper studies the optical behavior of the poly-Si/dielectric filmstack from 190 nm to 900 nm and the physical properties of the poly-Si layer. A more accurate modeling method is proposed to characterize the poly-Si and its top roughness layer using effective medium approximation (EMA) models. Using the new model, both a spectroscopic ellipsometer (SE) and a multi-angle multi-wavelength laser ellipsometer (MWLE) were employed to measure wafers with different poly-Si and gate oxide thicknesses. TEM was used to characterize the film thickness while roughness was determined using AFM. Good correlation was obtained between the TEM, AFM, and ellipsometry results. Excellent repeatability (0.04 Å 1σ on a 15 Å gate oxide for 10 days) and across the wafer uniformity (0.2 Å 1σ for a 49-point map) were also achieved when measuring gate dielectric films under the poly-Si with the MWLE. INTRODUCTION In the continuing quest to produce smaller, faster, semiconductor devices, transistor gate thicknesses have been shrinking at an increasing rate.1 Advanced methods for producing ultrathin gates deposit both the gate dielectric and the poly-Si gate electrode in a single cluster tool. This avoids the opportunity for MAC adsorption between the two layers and is more efficient, because the cycle time in a cluster tool can be up to 90% less than traditional processing and cluster tools require minimal operator support .2 Precisely controlling the thickness of ultrathin SiO2 gate dielectric films is critical for high yield advanced generation semiconductor manufacturing. Measuring the thickness of ultrathin gate oxides under a thick layer of poly-Si (GUPy) at the repeatability required for process control has been a difficult metrology challenge. Figure 1 shows a typical TEM image of a poly-Si (1500 Å) on SiO2 (1000 Å) filmstack. Poly-Si consists of amorphous silicon and polycrystalline silicon. The effective medium approximation (EMA) model has been used very successfully to model the poly-Si layer. With the EMA model, the volume fraction of the a
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