Investigation of Quasi-Breakdown Mechanism in Ultra-Thin Gate Oxides
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ABSTRACT The conduction mechanism of quasi-breakdown (QB) for ultra-thin gate oxide has been studied in dual-gate CMOSFET with a 3.7 nm thick gate oxide. Systematic carrier separation experiments were conducted to investigate the evolutions of gate, source/drain, and substrate currents before and after gate oxide QB. Our experimental results clearly show that QB is due to the formation of a local physicallydamaged-region (LPDR) at Si/SiO 2 interface. At this region, the effective oxide thickness is reduced to the direct tunneling (DT) regime. The observed high gate leakage current is due to DT electron or hole currents through the region where the LPDR is generated. Under substrate injection stress condition, there is several orders of magnitude increase of 1,,,b (1,/d) at the onset point of QB for n(p) - MOSFET, which mainly corresponds to valence electrons DT from the substrate to the gate. Consequently, cold holes are left in the substrate and measured as substrate current. Under gate injection stress condition, there is sudden drop and even change of sign of lsub (1Id) at the onset point of QB for n(p)-MOSFET, which corresponds to the disappearance of impact ionization and the appearance of hole DT current from the substrate to the gate. In the LPDR region, the damaged structure may have two or multi metastable states corresponding to different effective oxide thickness. The thermal transition between two or multi metastable states leads to random telegraph switching noise (RTSN) fluctuation between two or multi levels.
INTRODUCTION The integrity of ultra-thin gate oxide is one of the most crucial reliability issues for ULSI (Ultra-Large Scale Integrated) circuits. When the gate oxide is thinner than 5 nm, a new anomalous degradation mode has been reported over the past few years, referred to as quasibreakdown (QB) [1], or B-mode SILC [2,4], or soft-breakdown [3] indistinctly. Typical features of QB are high gate leakage current at low oxide field, the large gate signal fluctuations [1-9], and several orders of magnitude increase of substrate current in n-MOSFET after QB [1,7]. Several models have been proposed to explain the QB conduction mechanism [1,3,4]. Although there is consensus that QB is a localized phenomenon in a very small area [1-9], however, there is no generally accepted model of the QB conduction mechanism, giving an overall explanation of major observations under the QB. In this paper, a systematic and thorough investigation has been made, using constant current stress and carrier separation measurements [1 0-12,14] to both n- and p-MOSFETs. All experimental results strongly support that QB is due to the formation of a local physically-damaged-region (LPDR) at Si/Si0 2 interface. At this region, the effective oxide thickness is reduced to the direct tunneling (DT) regime[1].
EXPERIMENTAL AND NOTATIONS The MOSFETs used in our experiments are dual gate CMOS devices (p+-polysilicon gate for p-MOSFETs and n+-polysilicon gate for n-MOSFETs) fabricated by 0.18jtm design rule technology with a 3.7 n
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