Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology
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Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology Trapti Sharma1
· Laxmi Kumre1
Received: 16 March 2019 / Revised: 25 November 2019 / Accepted: 26 November 2019 © Springer Science+Business Media, LLC, part of Springer Nature 2019
Abstract This article presents the low-power ternary arithmetic logic unit (ALU) design in carbon nanotube field-effect transistor (CNFET) technology. CNFET unique characteristic of geometry-dependent threshold voltage is employed in the multi-valued logic design. The ternary logic benefit of reduced circuit overhead is exploited by embedding multiple modules within a block. The existence of symmetric literals among various single shift and dual shift operators in addition and subtraction operations results in the optimized realization of adder/subtractor modules. The proposed design is based on the notion of multiplexing either arithmetic, logical or miscellaneous operations, depending upon the status of input selection trits. The results obtained by the synopsis HSPICE simulator with the Stanford 32 nm CNFET technology illustrate that the proposed processing modules outperform their counterparts in terms of power consumption, energy consumption and device count. The proposed methodology leads to saving in power consumption and energy consumption (PDP) of 62% and 58%, respectively, on the benchmark circuit of the ALU [full adder/subtractor (FAS)]. Furthermore, for the 2-trit multiplier design, the enhanced performance at the architecture and circuit level is achieved through the optimized designs of various adder and multiplier circuits. Keywords Carbon nanotube field-effect transistor (CNFET) · Multi-valued logic design · Ternary ALU · Nano-technology · Low power
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Trapti Sharma [email protected] Laxmi Kumre [email protected]
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Department of Electronics and Communication Engineering, Maulana Azad National Institute of Technology, Bhopal, India
Circuits, Systems, and Signal Processing
1 Introduction Digital computation using binary logic has a serious concern in terms of interconnect complexity with the emergence of VLSI technology and circuit density [10]. Interconnects are the main source of power dissipation within a VLSI chip and comprises of 70% of total on-chip capacitance [16]. Moreover, scaling down the feature size into a nano-meter regime, several reliability and performance issues, restricts their usage in the implementation of energy-efficient digital designs. The solution is to perform computation using non-silicon devices exploiting multi-valued logic (MVL) systems. As MVL uses more than two logical levels, therefore, it facilitates the transmission of more amount of information over a single wire than binary logic, subsequently reduction in the amount of on-chip and off-chip interconnections have been observed. The MVL designs offer the benefits in terms of reduced chip area, increased data density with faster serial transmission and improved computational capability of the integrated circuits. Therefore, it helps to attai
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