Epitaxial Growth of III-V Nanowires on Group IV Substrates
- PDF / 2,398,313 Bytes
- 12 Pages / 612 x 792 pts (letter) Page_size
- 84 Downloads / 264 Views
1068-C02-04
Epitaxial Growth of III-V Nanowires on Group IV Substrates Erik Bakkers1, Magnus Borgstrom1,2, and Marcel Verheijen1 1 Philips Research Labs, Eindhoven, 5656AE, Netherlands 2 Solid State Physics, Lund University, Lund, Sweden ABSTRACT Semiconducting nanowires are emerging as a route to combine heavily mismatched materials. The high level of control on wire dimensions and chemical composition makes them promising materials to be integrated in future silicon technologies as well as to be the active element in optoelectronic devices. In this article, we review the recent progress in epitaxial growth of nanowires on noncorresponding substrates. We highlight the advantage of using small dimensions to facilitate accommodation of the lattice strain at the surface of the structures. More specifically, we will focus on the growth of III–V nanowires on group IV substrates. This approach enables the integration of high-performance III–V semiconductors monolithically into mature silicon technology, since fundamental issues of III-V integration on Si such as lattice and thermal expansion mismatch can be overcome. Moreover, as there will only be one nucleation site per crystallite, the system will not suffer from antiphase boundaries. Issues that affect the electronic properties of the heterojunction, such as the crystallographic quality and diffusion of elements across the heterointerface will be discussed. Finally, we address potential applications of vertical III–V nanowires grown on silicon. INTRODUCTION “Epitaxy” is derived from the Greek word meaning “ordered upon” and is the crystalline deposition of material on a substrate with identical lattice structure and orientation. For heteroepitaxial growth, materials with different lattice parameters are combined. If the lattice mismatch between the deposited film and the substrate is large, typically a few percent, misfit dislocations can be incorporated near the interface. Alternatively, adlayers may form threedimensional nuclei to release the strain in order to minimize the energy in the system, at the cost of creating more surface. With the development of the vapor–liquid–solid (VLS) wire growth method in 1964,1 it has become possible to vary the chemical composition within a nanowire. With this method thin semiconducting nanowires are grown from a catalytic metal particle. The small diameter (typically some tens of nm) results in effective strain release circumventing the usual requirement of lattice matching. Several groups have recently shown that such heteroepitaxial junctions can be defined in nanowires in the longitudinal (axial)2–6 direction as well as in the radial6–11 direction for different III–V compound semiconductors and for the Si/Ge system. These different materials can have a substantial lattice mismatch and the crystal lattices will be elastically deformed near the heterointerface. Such crystal deformations can be relieved at the surface for small enough wire diameters. If the lattice strain is totally accommodated by elastic deformations, the in
Data Loading...
