Evaluation of the modified edge lift-off test for adhesion characterization in microelectronic multifilm applications
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Eric G. Liniger and Xiao Hu Liu I.B.M. Research, P.O. Box 218, Yorktown Heights, New York 10598-0218 (Received 24 January 2000; accepted 20 October 2000)
The modified edge lift-off test (MELT) has gained enough acceptance in the community for evaluating interfacial adhesion that there is now commercial equipment for automating the test. However, there are several experimental and mechanics assumptions of the test that may provide unexpected outcomes. Experimental data suggested that for crack lengths greater than 5% of the film thickness the energy release rate was independent of crack length, contradicting the rule of thumb suggesting that the crack length should be greater than 10–20 times the film thickness to obtain a steady-state energy release rate in the edge crack problem. Finite element simulations not only corroborated the experimental observation but seemed to indicate that the crack length required for steady-state conditions was a function of the relative Young’s moduli for the film and substrate. It was also shown via an analytical model that plate bending (commonly neglected) can significantly affect the energy release rate in the MELT and lead to incorrect conclusions regarding the reliability of an interface.
I. INTRODUCTION
The microelectronics industry is vigorously seeking an adhesion test that (i) is simple in preparation, (ii) is easily modeled, (iii) is elastic, and (iv) produces results that are readily applied to the elaborate interconnect structures that exist in the back end of the line (BEOL). There are numerous tests available as commercial products or as methods in the literature that address adhesion quality and meet some of the criteria above, but no single method has been recognized as the “best” method. The complicated three-dimensional nature of a semiconductor device is difficult to model, but it is reasonable to assume that a delamination proceeds by the initiation of a crack at a processing flaw and the subsequent propagation of that flaw along an interface. The difficulty in using any of the adhesion characterization methods to simulate a delamination in an actual device lies in understanding how the results from a simplified test structure relate to the behavior of a complex structure. One is confronted with the question of which test is the most appropriate. In a semiconductor device cracks propagate under the influence of stresses due to processing, or as a result of performing the numerous tests required by the industry to insure product reliability. Recognizing that
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Address all correspondence to this author. e-mail: [email protected] J. Mater. Res., Vol. 16, No. 2, Feb 2001
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the available tests vary in several aspects affecting the state of stress at a crack tip, including geometry, temperature, and mode mixity, one can attempt to match a test with the state of stress in a device. It is more generally the case, however, that one assumes the best interface in any one adhesion test will perform the best in a
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