Extrinsic Performance Limitations of AlGaN/GaN Heterostructure Field Effect Transistors
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Cite this article as: MRS Internet J. Nitride Semicond. Res. 4S1, G6.35 (1999)
ABSTRACT Extrinsic effects on the DC output characteristics of AlGaN/GaN HFETs with lllm gate lengths are examined. The devices investigated were fabricated on MOCVD-grown AIGaN/ GaN heterostructures on sapphire substrates. An analytical model that takes into account parasitic resistances and thermal effects is constructed, and its results are compared with experimental data. With parameters determined from characterization experiments on the same wafer and from independent theoretical results, the agreement between the data and the model predictions is found to be very good. The model is then applied to performance predictions for devices with improved series resistances and heat sinking.
INTRODUCTION The group Ill-nitride compound semiconductors have considerable potential for the fabrication of high frequency/high power electronic devices. Progress in the growth and process technology of these materials has recently led to the demonstration of very impressive results for the output current density, the gain cut-off frequency, and the output power density of AlGaN/ GaN heterostructure field effect transistors (HFETs).[I,2,3] These encouraging results notwithstanding, the device design and the fabrication techniques are still far from optimized. For example, contact resistances are relatively large (compared to conventional Ill-V materials) and deleterious thermal effects are likely to limit the performance of the HFETs at high voltages and currents. This is particularly the case for devices fabricated on sapphire substrates, due to that material's relatively low thermal conductivity. In this communication extrinsic effects that limit the performance of AIGaN/GaN HFETs are examined in the framework of an analytical model. The results are compared with experimental data from AlGaN/GaN HFETs. It is found that significant improvements in output current can be expected if the heat generated in the devices is removed effectively (for example by a flip-chip bonding technique, or by the use of a substrate with high thermal conductivity) and if the source and drain series resistances can be reduced.
DEVICE STRUCTURE The IlI-nitrides used in this study were grown by MOCVD on sapphire substrates. The G 6.35 Mat. Res. Soc. Symp. Proc. Vol. 537 © 1999 Materials Research Society
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Figure 1: Schematic HFET diagram.
Figure 2: Calculated values of Ad and electron concentration in the lowest subband as a function of the total sheet carrier density.
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material structure consisted of an AIN nucleation layer, followed by 31.tm of undoped GaN and 200A of nominally undoped Al 0 .3Ga 0 .7 N. Ohmic contacts were formed using alloyed Ti/Al/Ni/ Au, and the gate metallization was Pt/Au. Device isolation was accomplished through the use ECR dry etching. The source-to-drain spacing was 51tm and the gate length was lgtm.
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