Thermal Modeling of III-nitride Heterostructure Field Effect Transistors
- PDF / 321,464 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 90 Downloads / 177 Views
Thermal Modeling of III-nitride Heterostructure Field Effect Transistors T. Li, P.P. Ruden, J.D. Albrecht,* M.G. Ancona,* and R. Anholt+ Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 *Electronics Science and Technology Division, Naval Research Laboratory, Washington, DC 20375 + Gateway Modeling Inc., 1604 East River Terrace, Minneapolis, MN 55414 ABSTRACT The output characteristics of AlGaN/GaN semiconductor heterostructure field effect transistors are strongly dependent on the ambient temperature of the channel region due to relatively large variations in the electron drift velocity with temperature. A model to simulate the heat flow in AlGaN/GaN HFETs on sapphire and SiC substrates is presented. The nonlinearity of the problem arising from the temperature dependencies of the III-nitride and substrate thermal conductivities is examined through the technique of self-consistent boundary conditions. It is found that the use of the linearizing Kirchhoff transformation is a good approximation for these systems. Alternative approaches of heatsinking the devices from the top of the wafer are explored also. INTRODUCTION Gallium Nitride is considered to be a good candidate material for high power, high frequency electronic devices.1 The large band gap ensures relatively large breakdown voltages and high electron drift velocities allow for short transit times. Furthermore, the relatively close lattice match to AlGaN alloys, which have an even larger band gap, enables the fabrication of heterostructure transistors with excellent carrier velocities. In the absence of native substrates, III-nitride heterostructures are usually grown on either sapphire or SiC substrates. A critical challenge for the successful use of III-nitrides in power heterostructure field effect transistors (HFETs) is the effective removal of the heat generated by the power dissipated in the channel. The standard approach is to heatsink the devices at the bottom of the substrates. However, it has been shown that in the case of sapphire this method is rather inefficient, leading to clear thermal limitations on the current achievable.2,3 SiC substrates offer the advantage of higher thermal conductivity and, hence, more effective heatsinking. Removal of the heat through thermal contacts on the topside of the wafer appears advantageous due to the close proximity of these contacts to the heat generating channel region.4 A difficulty with this approach is the need to separate the thermal contacts from the electrical contacts. Although reasonable qualitative results can be obtained from two-dimensional heat flow models, accurate analysis for HFET structures that are heatsunk through the substrate requires a three-dimensional treatment since gate widths typically are comparable to the substrate thickness. In addition, the heat flow problem is intrinsically non-linear due to the temperature dependencies of the thermal conductivities of the III-nitride epi-layers, the substrates, and the metal contact layers. In thi
Data Loading...
