Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Te
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Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique Inamul Hussain1
· Saurabh Chaudhury1
Received: 21 November 2019 / Revised: 10 September 2020 / Accepted: 13 September 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract For computational arithmetic, a full adder is the primary logic units in VLSI applications. A new full adder circuit design has been presented in this article which is based on input switching activity pattern and gate diffusion input (GDI) technique. The adder has been designed in two stages. The first stage is an XOR–XNOR module, whereas, the final stage is for the required outputs. By using the switching activity pattern of inputs and GDI techniques at each stage, the switching activities of the transistors have been minimized. This improves delay, power consumption and computational complexity. The adder has been designed and evaluated by using the synopsis tool and compared with different existing adder cells found in the literature. It is found that the presented adder shows an improvement at least 72.86% and 66.67% in terms of speed and energy consumption, respectively. Extensive performance analyses of the full adder have also been evaluated at 32 nm CMOS and 32 nm CNFET technology node which shows promising performances in both the technology nodes. Keywords Delay · GDI · Low power · MUX · Power-delay product · Speed
1 Introduction In the fast-growing and diversified applications of VLSI circuits and systems, an adder plays a vital role. The main uses of adder circuits are in digital signal processing (DSP) architectures, microprocessors, image processors, etc. [5, 41, 44]. Though the prime use of adder is to add binary numbers, it is also used in multiplication, address calculation, etc. [2, 30]. Adders mostly reside in the critical path of the data flow.
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Inamul Hussain [email protected] Saurabh Chaudhury [email protected]
1
Department of Electrical Engineering, National Institute of Technology Silchar, Silchar, India
Circuits, Systems, and Signal Processing
Hence, the performance of the adder circuit eventually leads to enhance the overall performance of the system as a whole. Therefore, it becomes the prominent goal of design researchers to design the adder circuit for better performance [37, 25]. Nowadays, the users of portable battery-operated devices such as mobile phones, computers, laptops, etc. [24] have been increasing abruptly and so low-power highspeed design is the need of the time [33]. Since high speed and low power are inversely proportional to each other, one has to find a trade-off between them [22]. It is therefore one of the most thought-provoking approaches to design a full adder circuit with low power consumption and high speed of operation [6, 12, 46]. There are many design approaches [48] for full adders. Each design has its own merits and demerits [27]. One of the oldest full adders (FA) is based on complementary metal–oxide–semiconductor
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